Just about every modern MCU family has a USB peripheral. Since USB is a standard, you might expect that all USB implementations are the same. If so, you would be surprised by the wide variety of implementations that meet the standard, but also offer additional capabilities and features that might just make a particular MCU perfect for your next design. This article will describe some of the differentiated USB features you will find in popular MCU families. Once you understand some of the key differences you can better look for the implementation that will offer the perfect fit for your next design.
The Universal Serial Bus, or USB, has grown in popularity due to its simple physical layer interface, its flexibility, and ease of integrating – both at the hardware and software levels. Standardized and integrated connectors make it easy to interface an MCU to the USB cable and common drivers and application program interfaces, or APIs, make it easy to access the data and control elements needed to transfer and receive information packets over the USB connection. Readily available reference designs, evaluation boards, and code examples further simplify MCU-based implementations. The recent introduction of the USB 3.1 standard, with a data signaling rate of up to 10 Gbit/s illustrates that the standard continues to evolve and is likely to be around for many, many more years.
USB uses an asymmetrical topology, consisting of a host at the top of the connection “pyramid” that manages the entire network. Downstream USB ports (commonly called devices or functions) all connect into the host either directly or via intermediate hubs that can extend the network in a star topology. A host may have multiple host controllers with each controller managing up to 127 ports. USB communication uses pipes, or logical channels, that connect between a host controller and a device endpoint. A USB device can have up to 32 endpoints (16 in and 16 out). There are two types of pipes: a stream, used for data transfers, and a message, used for short commands and status transfers. Data transfers can be either isochronous (with a guaranteed data rate), interrupt transfers (when quick, low-latency transfers are needed), or bulk transfers (typically used for file transfers where latency and data rates are not critical).
One of the more useful aspects of the USB standard is that there are multiple data rates possible (Low speed at 1.5 Mbit/s, Full speed at 12 Mbit/s, High speed at 480 Mbit/s, SuperSpeed at 5 Gbit/s, and SuperSpeed+ at 10 Gbit/s) and the host can determine data rates for each device using a special enumeration process. This simplifies connection management and makes it easy for the application to focus on just transferring data, not managing the establishment of the low-level physical connections.
Several Product Training Modules are available from Hotenda that discuss the USB standard in significant detail (from FDTI and Wurth Electronics, among others) if the reader wishes to dig deeper. However, for the purposes of this article, the above description should be sufficient to allow us to look at some of the different features and capabilities of MCU-based USB peripherals to better match the requirements of a particular application with an optimal USB-implementation feature set.
With some of the basics of USB understood we can begin to look at the different types of implementations MCU vendors have provided in their devices. Since MCUs are often found controlling USB peripheral devices such as sensors, pointing devices, and audio devices (just to name a few) as opposed to the host controllers more often found in PCs and handhelds, we will start by looking at an example function implementation found in the Spansion FM3 MCU family, in particular the Spansion MB9AF3 MCU.
The Spansion MB9AF3 MCU uses an ARM-Cortex-M3 CPU and has several advanced peripherals, including motor-control timers, high-speed ADCs, UART, SPI, I2C, DMA, and an external bus interface. A USB peripheral has both a Host and Function interface and the block diagram of the function is shown in Figure 1, below. The CPU interface, on the right side of the diagram, can access the endpoint buffers where data transfers are located. Movement into and out of the buffers are managed by the USB Data Controller (UDC) via the UDC interface. Interrupts can be used to notify the CPU of the status of data transfers and the CPU interface provides access to the buffers from either the CPU or the DMA controller.
Figure 1: Spansion MB9AF3 MCU USB function block diagram. (Courtesy of Spansion)
Key elements of the Spansion USB implementation are the source for the USB clock, the number of Endpoint Buffers, and DMA access to the endpoint buffers. These features can vary between different MCU vendors since they are not specified by the USB standard. For example, the USB clock is sourced by an on-chip PLL that can use the main clock source of the MCU. This eliminates the need for an external clock reducing component count. Not all USB peripherals include this capability.
From Figure 1 you will also see that there are six endpoint buffers. The number of buffers available varies widely from implementation to implementation. For simple applications, a small number of buffers could be sufficient, but there may be requirements for multiple buffers, perhaps because there are multiple elements (for example, several different sensors managed by the MCU) or because multiple buffers would simplify the software implementation by separating different applications of a single peripheral.
Finally, a common area of differentiation between USB implementations involves the use of DMA. Often it is much more efficient to have endpoint buffers managed independently from the CPU so that the CPU can be doing other, more complex tasks, or can be put in a low-power state until enough data is available to begin processing. The MB9AF3 MCU provides access to the endpoint buffers to the DMA controller and also provides several interrupts that can be used to more easily manage buffer transfers. Look for these capabilities when power efficiency is critical to your application.
The number of endpoints you require can be a key differentiator when selecting your USB peripheral. The amount of flexibility you have with each endpoint can be an important factor in your selection, too. For example, the Cypress PSoC CY8C24794 has a USB peripheral with five endpoints and each can be separately assigned to respond to Interrupt, Bulk, or Isochronous IN or OUT requests. Figure 2 shows the variety of tasks that can be assigned to each endpoint. This level of selectivity avoids a significant amount of processor overhead that would otherwise be needed to determine the type of task and then transfer control to the needed routine.
Figure 2: USB Operating Mode Table for the Cypress PSoC CY8C24794. (Courtesy of Cypress)
The Cypress USB implementation uses a shared memory to store the endpoint data and this could cause an access bottleneck, but the use of a PSoC Memory Arbiter (PMA) prioritizes access between the processor and the USB peripheral. This guarantees that a continuous stream of move instructions by the processor will be serviced even while USB traffic is processed at the maximum rate.
The USB PMA is flexible enough so that endpoint data does not need to be processed before the next USB packet is received. This is done by simply changing the channel’s write location or read location register value. For example, when an interrupt is received indicating that a packet has been received, rather than processing the data and then enabling the endpoint to receive more data, you can simply change the write address for the PMA channel used by the endpoint to a free area of the USB RAM. By doing this, you allow the USB SIE to receive more data while the M8C is processing the previously received data. A similar method may be used to prepare data to be sent by way of an IN transaction.
When comparing endpoint implementations make sure you look not only at the number of endpoints supported, but also at the amount of flexibility and software support the USB peripheral offers. This can improve performance, reduce power consumption, and simplify coding.
USB on the go
USB has also evolved to make it easy to create intelligent USB devices that can connect in either a host or function mode dynamically. This “On the Go” capability makes it possible to use the device as a peripheral (perhaps as a storage device) and then as a host (perhaps to control and power a sensor that records heart-rate activity). This capability is particularly useful in a variety of IoT applications. The Microchip DSPIC33EP256 MCU, for example, supports USB Host, Device and On the Go modes. In many cases low-power operation is important for On the Go applications so it can be important to see what low-power facilities are available for the USB peripheral.
The Microchip DSPIC33EP256 MCU allows the USB peripheral to operate even in some low-power modes. For example, the peripheral can still operate when the CPU is placed in the Idle mode. In the Idle mode the CPU clock is gated off, and this reduces dynamic power considerably. The USB module can continue to operate when the CPU is idle and once a message that needs CPU intervention is received, the CPU can be brought out of Idle. The USB peripheral and the CPU can both be put in an even lower power state, Sleep, where even more power is saved. The USB activity interrupt can be used to wake the device from the Sleep mode whenever there is bus activity on the USB bus.
Another capability you might require from your USB peripheral is advanced testing features. In particular, if you are using USB for the first time some of you might want to include board-level testing functions specifically for the USB port. The Microchip DSPIC33EP256 MCU has a special USB testing mode that can generate a continuous test pattern on the USB output that is useful for board-level tests. As seen in Figure 3 this test mode generates continuous J-K/J-K bit sequences to toggle the USB outputs generating a simple “Eye Pattern” commonly used to test signal integrity.
Figure 3: Microchip DSPIC33EP256 MCU USB Test Mode. (Courtesy of Microchip)
USB in high-end MCUs
USB is not only found in low- and medium-end MCUs, it is a very useful interface for high-end devices as well. For example, the Texas Instruments F28M35H52C1RFPT is a dual-core MCU with very advanced processing capabilities and it includes a USB peripheral with On the Go capability. As seen in the block diagram of the F28M35H52C1RFPT (Figure 4), the USB peripheral, in the upper left of the diagram, is connected to the ARM Cortex-M3 CPU via an AHB bus accessed from an AHB bus matrix.
Figure 4: Texas Instruments F28M35x Concerto MCU Block Diagram. (Courtesy of Texas Instruments)
The ARM Cortex-M3 CPU acts as the channel controller, responsible for managing all the communications ports. This is an important capability when USB is included on high-end devices so that USB traffic can be prioritized correctly with respect to all the other, competing, communications ports. For example, often the USB port is used for external file storage and data-transfer activity may need to be made a very high priority so that processing does not stall for lack of data.
There are many different approaches to USB implementations and it is important to understand some of the key features and differentiated functions offered by various MCU Families. It is much easier to find the right fit for your next USB application when you know some of the most common and important differences.
For more information about the parts discussed in this article, use the links provided to access product pages on the Hotenda website.