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USB 3.0 - Are We There Yet?

SuperSpeed USB may be slow out of the blocks, but with a 10x speed advantage and lower power profile than its predecessors, its compelling advantages make it look like a sure winner.

If there was a universal serial bus in 1995, it was RS-232. Every PC in the world had one, although you could connect only one device to it at a time. Reconfiguring the port for new devices and/or applications required you to either be a “power user” or have an engineering degree.

In January 1996, Intel introduced the Universal Serial Bus (USB), a bidirectional, low-cost, low- to mid-speed peripheral bus that could support as many as 127 devices, all of which could be added to the bus in “plug-and-play” (initially “plug-and-pray”) fashion. USB 1.0 supported a data transfer rate of 12 Mb/s, which worked well for disk drives. In 1998, USB 1.1 added a slower (1.5 Mb/s) rate to support keyboards, mice, and other human-interface devices (HID).

Addressing the need for speed, the USB 2.0 specification was released in 2000 and standardized in 2001, promising a data rate of 480 Mb/s. However, because of the overhead involved in the protocol and USB’s heavy reliance on the processor for transaction arbitration and scheduling, speeds closer to half that rate were more typical. Still, a theoretical 40x increase in bus speed in four years was pretty impressive.

USB has since become the most successful PC peripheral interconnect ever defined, with over 10 billion USB 2.0 products installed today, a number that is rising rapidly. In-Stat predicts that nearly 4.5 billion USB ports will ship in 2014, of which 1.7 billion will support the new “SuperSpeed” USB 3.0 spec.

Facing competition from other high-speed interconnect protocols (Figure 1), like 400 and 800 Mbps IEEE-1394 (FireWire) and HDMI (both of which targeted high-data rate streaming of video), the USB Implementers Forum (USB-IF) formalized the specification for USB 3.0 in 2008, which promises a “SuperSpeed” data rate of 5 Gb/sec, a 10x improvement over USB 2.0.

Design goals

With USB 2.0 having become universal, the key goal was to make it faster. Since smart phone users can now sideload video files ten times faster, this will supposedly keep HDMI or FireWire sockets from proliferating on these devices.
Figure 1: Communications protocols speed comparison.

The primary goals for USB 3.0 are to:
  • Preserve the USB model of smart host and simple device.
  • Leverage the existing USB infrastructure. This means maintaining the same software architecture and easing the migration from legacy products.
  • Improve power management.
  • Maintain ease-of-use.
  • Preserve users’ investment in USB 2.0 devices.
With minor modifications, USB software stacks will continue to recognize the following three device classes:
  • Communications Device Class (CDC), which presents the USB port to an application as a standard COM port. Supporting bulk transfers, the CDC provides high-bandwidth with a reasonable amount of simplicity.
  • Human Interface Device (HID) Class, which supports mice, keyboards, touchscreens and other input devices. Bandwidth is limited to 64 kb/s.
  • Mass Storage Class (MSC), which supports moving large amounts of data to and from flash drives, digital cameras, and flash card readers.
USB 3.0 is clearly overkill for HID applications, but it’s definitely a new contender for embedded CDC and MSC applications, particularly those involving streaming high-definition video. Its power advantage over legacy USB makes it a serious consideration for portable devices.

Architectural innovations

Achieving a 10x speed improvement while reducing power consumption involved making serious architectural changes to both the protocol and associated hardware. At the same time, some trade-offs (and clever workarounds) were necessary to maintain backward compatibility with legacy USB 2.0 products.

For starters, USB 3.0 maintains the same tiered star topology as USB 2.0, maintaining compatibility by adding two more twisted pairs to the cable to supplement the USB 2.0 data pair, which is left untouched. The two additional signal pairs create a dual simplex SuperSpeed data path, with one pair for transmit and one for receive. This enables backward compatibility by including both SuperSpeed and non-SuperSpeed bus interfaces.

Figure 2: USB 3.0 dual-bus architecture. (Used with permission from USB-IF).

Polling is also eliminated. A USB 2.0 host continuously polls all peripheral devices to see if they have data to send to the host controller. All devices must therefore be on at all times, which not only wastes power but adds unnecessary traffic to the bus. In USB 3.0, polling is replaced by asynchronous notification. The host waits until an application tells it that there is a peripheral with data it needs to send to the host. The host then contacts that peripheral and requests that it send the data. When both are ready, the data is transferred.

USB 2.0 is inherently a broadcast protocol. USB 3.0 uses directed data transfer to and from the host and only the target peripheral. Only that peripheral turns on its transceiver, while others on the bus remain in powered-down mode.

Numerous innovations in the USB 3.0 architecture set it apart from its predecessors (Figure 3).

Figure 3: USB 3.0 logical architecture. (Used with permission from USB-IF).


The SuperSpeed USB physical connection is comprised of two differential data pairs: one transmit path and one receive path, both operating at 5 GB/s. Each differential link is initialized by enabling its receiver termination. In the absence of signaling, low frequency periodic signaling (LFPS) is used to signal initialization and power management information. Data is packetized and passed directly to the intended receiver. Since USB 3.0 does not include a reference clock, each PHY has its own clock domain with spread spectrum clocking (SSC) modulation. The transmitter encodes data and control characters into symbols using an 8b/10b code, ensuring enough transitions that the receiver can accurately recover clock and data.

Link layer

SuperSpeed USB moves firmly into the realm of high-speed packet processing. The link layer handles link initialization and flow control, packet framing, link power management and error detection, and recovery. There are separate Link Management Packets (LMP), Transaction Packets (TP), Isochronous Timestamp Packets (ITP) and Data Packets (DP); all start with a distinct 14 byte header packet, consisting of 12 bytes of header information and a two byte CRC-16 code. This is not your dad’s USB.

Protocol layer

SuperSpeed USB is not a polled protocol, as devices may asynchronously transmit notifications to the host. Host-transmitted protocol packets are routed through intervening hubs, taking a direct path to a peripheral device. The transmitter can transmit multiple bursts of back-to-back sequences of data packets, while the receiver can simultaneously transmit data acknowledgements without interrupting the burst of data packets. This is a far more efficient use of bus bandwidth than the half-duplex, non-bursting nature of traffic on earlier USB buses.

Table 1 summarizes the main differences between high-speed USB 2.0 and SuperSpeed 3.0.

Power management

First, SuperSpeed makes more power available to connected devices. The amount of power available on the USB bus (for recharging cell phones and other portable devices, for example) is increased from 5 V at 500 mA in USB 2.0 to 5 V at 900 mA for USB 3.0. This is a distinct advantage as more portable devices have come to rely on the USB bus not just for data transfer but also for battery recharging.


USB 2.0

USB 3.0

Data rate

Low-speed (1.5 Mbps), full-speed (12 Mbps), and high-speed (480 Mbps).

SuperSpeed (5.0 Gpbs)

Data interface

Half-duplex, two-wire differential signaling. Unidirectional data flow with negotiated directional bus transitions.

Dual-simplex, four-wire differential signaling seperate from USB 2.0 signaling. Simultaneous bi-directional data flows.

Cable signal count

Two: two for low-/full-/high- speed data path.

Six: four for SuperSpeed data path. Two for non-SuperSpeed data path.

Bus transaction protocol

Host directed, polled traffic flow. Packet traffic is broadcast to all devices.

Host directed, asynchronous traffic flow. Packet traffic is explicitly routed.

Power management

Port-level suspend with two levels of entry/exit latency. Device-level power management.

Multi-level link power management supporting idle, sleep, and suspend states. Link-, Device-, and Function- level power management.

Bus power

Support for low/high bus-powered devices with lower power limits for unconfigured and suspended devices.

Same as USB 2.0 with a 50% increase for unconfigured power and 80% increase for configured power.

Port state

Port hardware detects connect events. System software uses port command to transitions the port into an enabled state (USB data communication flows).

Port hardware detects connect events and brings the port into operational state ready for SuperSpeed data communication.

Data transfer types

Four data transfer types: control, bulk, Interrupt, and lsochronous.

USB 2.0 types with SuperSpeed constraints. Bulk has streams capability.

Table 1: USB 2.0 versus 3.0. (Used with permission from USB-IF).

More importantly, SuperSpeed USB enables considerable power savings by enabling both upstream and downstream ports to initiate lower power states on the link. In addition, multiple link power states are defined, enabling local power management control and, therefore, improved power usage efficiency. Eliminating polling and broadcasting also went a long way toward reducing power requirements. Finally, the increased speed and efficiency of USB 3.0 bus, combined with the ability to use data streaming for bulk transfers, further reduces the power profile of these devices. Typically, the faster a data transfer completes, the faster system components can return to a low-power state. The USB-IF estimates the system power necessary to complete a 20 MB SuperSpeed data transfer will be 25 percent lower than is possible using USB 2.0.

The SuperSpeed specification brings over Link Power Management (LPM) from USB 2.0. LPM was first introduced in the Enhanced Host Controller Interface (EHCI) to accommodate high-speed, PCI-based USB interfaces. Because of the difficulty of implementing it, LPM was slow to appear in USB 2.0 devices. It is now required in USB 3.0 and for SuperSpeed devices supporting legacy high-speed peripherals. LPM is an adaptive power management model that uses link-state awareness to reduce power usage.

LPM defines a fast host transition from an enabled state to L1 Sleep (~10 µs) or L2 Suspend (after 3 ms of inactivity). Return from L1 sleep varies from ~70 µs to 1 ms; return from L2 Suspend mode is OS dependent. The fast transitions and close control of power at the link level enables LPM to manage power consumption in SuperSpeed systems with greater precision than was previously possible.

Link power management enables a link to be placed into a lower power state when the link partners are idle. The longer a pair of link partners remain idle, the deeper the power savings that can be achieved by progressing from UO (link active) to Ul (link standby with fast exit) to U2 (link standby with slower exit), and finally to U3 (suspend). Table 2 summarizes the logical link states.

Link State Description Key Characteristics Device Clock Exit Latency
U0 Link active. - On N/A
U1 Link idle, fast exit. RX & TX quiesced On or Off µs
U2 Link idle, slow exit. Clock gen circuit also quiesced. On or Off µs-ms
U3 Suspend. Portions of device power removed. Off ms
Table 2: Logical link states. (Used with permission from USB-IF).

Most SuperSpeed devices, sensing inactivity on the link, will automatically reduce power to the PHY and transition from U0 to U1. Further inactivity will cause these devices to progressively lower power. The host or devices may further idle the link (U2), or the host may even suspend it (U3).

Both devices and downstream ports can initiate Ul and U2 entry. Downstream ports have inactivity timers used to initiate Ul and U2 entry. Downstream port inactivity timeouts are programmed by system software. Devices may have additional information available that they can use to decide to initiate Ul or U2 entry more aggressively than inactivity timers. Devices can save significant power by initiating Ul or U2 more aggressively rather than waiting for downstream port inactivity timeouts.

While the advantages of SuperSpeed USB are impressive, these devices are just beginning to appear in a world dominated by USB 2.0. For backward, compatibility SuperSpeed devices must support both USB 2.0 and 3.0 link speeds, maintaining separate controllers and PHYs for full-speed, high-speed and SuperSpeed links. By maintaining a parallel system to support legacy devices, SuperSpeed’s designers accepted higher cost and complexity as a price worth paying to avoid compromising the speed advantage of their new architecture.

Adoption ramp

No new standard, whatever its technical advantages, is adopted overnight. That is certainly true with USB 3.0, which needs to see a critical mass of devices in the field before it will take off. Since consumers have long been content with USB 2.0, and since SuperSpeed devices will initially be more expensive, consumers will need to be convinced of compelling application benefits before it is likely to see broad adoption. Streaming multimedia is almost undoubtedly the killer app that will make this happen.

One of the major things holding back USB 3.0 is the lack of support for it in core logic chipsets. Intel made much of its support for the standard at IDF 2009, and there was plenty of talk about it at the USB pavilion. However, at IDF 2010 Intel made no production silicon announcements—reportedly because of the difficulty of developing bug-free silicon—and there does not appear to be any plan to include it in either Sandy Bridge or Atom processors for the next year or so. Intel’s apparent hesitation about supporting the standard will clearly stall its adoption in the marketplace and give Intel-based embedded developers pause about including it in their designs. Despite its recent hesitation, Intel will almost undoubtedly support USB 3.0 by next year.

Meanwhile, the USB-IF announced more than 100 SuperSpeed-certified products at IDF 2010, so this train, while still getting up to speed, has clearly left the station. It is now up to embedded developers to determine whether USB 3.0 is appropriate for their applications, and if so, to get on board.