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The Evolving Face of Telecom Processing

The demands of telecom applications have seen microcontrollers evolve into quite specialized designs. Microcontrollers are used within the telecom network in many different ways, from several different varieties of network processors to dedicated multi-protocol processors.


By 2015, analysts expect 90% of the content viewed on mobile devices to be streaming video, while application downloads are expected to reach forty-seven billion per year. This is driving global data traffic to grow eighteen times by 2016, and as a result the carrier Ethernet equipment market is set to reach $40.2 billion by 2015.

As mobile broadband use driven by tablets and smartphones continues to grow, and networks transition from 2G/3G to LTE and LTE-Advanced, operators need cost- and power-efficient solutions to migrate backhaul from legacy systems to IP-based networks. Mobile backhaul networks move traffic between cellular base stations and the core of the wired network, and are under increasing pressure as mobile broadband traffic continues to grow.

All of this is putting increasing strain on the telecom infrastructure to deliver the processing power to handle all the data within the design constraints of the network. Power consumption is an increasingly important factor, as higher performance devices that are designed to handle the higher data rates also generate more heat. For the line cards in telecom systems, this is a major issue as cooling of the routers is a key cost for operators, and increased heat also reduces the reliability. For networks that have to be available 24 hours a day, 365 days a year, reliability is a key design issue.

All this necessitates a new generation of network processors, optimized for the handling of large amounts of data with the lowest possible power consumption. Multi-core designs are increasingly popular, with more functions, previously seen in enterprise networks, now becoming vital in the telecom infrastructure. Traditional telecom networks increasingly have to support the mobile phone networks and the vast amounts of new data being carried, so there is a rising demand for network processing functions through a typical network.

This vast boom in data is also driving more of the processing out to the edge of the network. Instead of having a big, centralized switch that handles everything, the use of IP protocols now allows the intelligence to be more widely distributed throughout the network. This allows some of the switching and routing to be kept local without having to go through the core network, easing congestion. However, this requires more intelligent processors in devices such as home gateways and even wireless access points.


The architecture of a telecom network can be crudely partitioned into the control and data planes. A simple differentiation is that switching happens in the data plane while routing – directing packets and performing operations on the data – happens in the control plane.

High-speed switching in the data plane requires highly customized high speed ASICs, and these are controlled by the network processors in the control plane. These processors also provide security for the headers, and sometimes data analysis through techniques such as Deep Packet Inspection. This can determine what the content of the packet is – whether it is video or more random data such as plain text. This is important in determining the priorities for the packets as they move through a switch. Video packets have to be prioritized to ensure that the quality of service is maintained, while other types of data can take a little longer to reach their destination. As line speeds in the core of the network increase, the time available to do this analysis reduces and more performance is needed. However, further out to the edge of the network, the line rates can be less and so there is potential to add intelligence in devices for the edge without having to have the highest possible performance, reducing the power consumption and the cost of both the device and the system.

All of this routing still requires access to the database of locations, so data handling within the device is a key element. Devices include hardwired processing blocks to handle the dedicated protocols used in the network.

Network processors

The telecoms routing functions are driving further down into the network as new standards such as 802.11ac wireless are requiring much higher line speeds of 450 Mbit/s. This is difficult to handle with traditional devices. Adding telecom routing functions into gateways in the home or wireless access points allows some of the IP traffic to be handled at the edge of the network, rather than having to travel all the way through, creating congestion.

Devices are adding more cores to handle this. These additional cores can be used as a control and management processors, or as integrated control and data path processors.

New devices are combining traffic management, security and packet processing capabilities, the bridging function of an Ethernet switch, and the transport and internetworking functions of a multiservice processor in a single device.

The processors are designed for mobile infrastructure applications such as indoor and outdoor microwave units, cell-site routers, packet transfer nodes and backhaul, providing lower power consumption, and space requirements by integrating packet processing, security and switching features which provide increased security and capabilities. Using the processor core and hardware accelerators provides programmable flexibility and deterministic performance and software support across a whole family. This is increasingly important for equipment developers who need to re-use code from one project across many others, whether they are for the core network or for the edge. A common instruction set architecture and set of peripherals is a key advantage in this situation.

“Managing costs while meeting the ever-increasing demand for mobile broadband is a key challenge,” said Mark Hung, research director at market researchers Gartner. “Operators will benefit from more integrated IC solutions for mobile infrastructure systems, as they can reduce cost while migrating to 4G networks.”

The Freescale QorIQ P2 is a PowerQUICC communications processor aimed at telecom infrastructure designs. Built using high-performance e500 Power Architecture cores, the devices are aimed at applications where the reliability, security and quality of service for every connection matters.

Figure 1: The QorIQ P2020 dual core network processor.

 The QorIQ P2 platform series, which includes the P2020 (dual-core processor) and P2010 (single-core processor) communications processors, delivers high, single-threaded performance per watt for a wide variety of applications in the networking, telecom, military, and industrial markets. The series delivers dual- and single-core frequencies up to 1.2 GHz on a 45 nm technology low-power platform.

The QorIQ P2020 and P2010 single- and dual-core products are pin-compatible with the QorIQ P1 platform products, offering four interchangeable, cost-effective solutions.

Scaling from a single-core processor at 533 MHz (P1011) to a dual-core processor at 1.2 GHz (P2020), the two QorIQ platforms together deliver an impressive 4.5x aggregate frequency range within the same pin-out. The devices in these two series are software-compatible, sharing the e500 Power Architecture core and peripherals, as well as being fully software compatible with the existing PowerQUICC processors.

This enables customers to create a product with multiple performance points from a single board design. The P2020 and P1020 dual-core processors support symmetric and asymmetric multi-processing, enabling customers to scale performance through either thread-level or application level parallelism.

An optional integrated security engine supports the cryptographic algorithms commonly used in IPsec, SSL, 3GPP and other networking and wireless security protocols. The 64-bit memory controller offers future-proofing against memory technology migration with support for both DDR2 and DDR3. It also supports error correction codes, a baseline requirement for any high-reliability system. Other memory types such as flash are supported through the 16-bit local bus, USB, SD/MMC and SPI.

The P2010 and P2020 processors integrate a range of interfaces, including SerDes, Gigabit Ethernet, PCI Express, RapidIO technology and USB. The three 10/100/1000 Ethernet ports support advanced packet parsing, flow control and quality of service features, as well as IEEE 1588 time stamping.

The processors are especially targeted at designs that have tight thermal constraints. With an available junction temperature range of -40°C to +125°C, the devices can be used in power-sensitive defense, aerospace and industrial applications, and less-protected outdoor environments. They enable various combinations of data plane and control plane workloads in networking and telecom applications that require higher performance, but want to avoid the complexity of partitioning the application across many cores.

The primary target applications are networking and telecom linecards. The P2 devices, with their low power budget and high single-threaded performance, are well suited for control plane applications.

Control plane applications tend to be more sequential in nature, and thus lose scaling efficiency with increasing number of threads or cores. The P2 series, with its low power, efficient, dual-issue out-of-order e500 core, Power Architecture technology, and high 1.2 GHz frequency, offers a level of single-threaded performance that is a perfect fit for control plane applications.

The networking line card requires an optimal combination of good performance to manage a large amount of control plane traffic balanced against low power and cost. With convenient I/O, flexible core configurations, and an on-board security block, the P2010 and P2020 processors are ideal for this application, which involves controlling ASICs, managing exceptions, and routing table maintenance.

The P2010 and P2020 processors are also suitable for Long Term Evolution (LTE) and WiMAX channel card applications. With dual-core performance in single-core power budgets, the P2 series facilitates the “flattening” of the wireless network hierarchy.

The dual Serial RapidIO interfaces allow direct connection to the DSPs (such as Freescale’s MSC8256 DSP) that implement Layer 1 processing as well as redundant backplane connections.

The dual P2020 and single P2010 Power Architecture e500 cores provide 36-bit physical addressing with double-precision, floating-point support and use a 32 KB L1 instruction cache and 32 KB L1 data cache for each core. With 800 MHz to 1.2 GHz clock frequency, there are three 10/100/1000Mbps enhanced three speed Ethernet controllers (eTSECs) with TCP/IP acceleration and classification capabilities. The high-speed interfaces support various multiplexing options, from four SerDes lines up to 3.125 GHz multiplexed across controllers, three PCI Express interfaces, two Serial RapidIO interfaces, and two SGMII interfaces for communications links between the control and data plane.

An integrated security engine (SEC 3.1) provides crypto algorithm support including 3DES, AES, RSA/ECC, MD5/SHA, ARC4, Kasumi, Snow 3G, and FIPS deterministic RNG, as well as single pass encryption and message authentication for common security protocols such as IPsec, SSL, SRTP, WiMAX.

The family has a roadmap forward with quad core designs built on a 28 nm process that are due to be available in 2013. These will allow the same software to run, providing scalability and longevity to system designs.

Multi-protocol processors

The big central network processor is not the only design approach. Freescale has tackled the power issue for multi-protocol processors with a low cost version of the well-known MC68302 Integrated Multiprotocol Processor (IMP). The MC68LC302 provides the functionality of the original 68302 with a static core for lower power consumption, a new timer and low power modes, but without the third serial communication controller (SCC). It is packaged in a low profile 100 TQFP that requires less board space than the regular MC68302, as well as making it suitable for use in height-restricted applications.

Figure 2: The MC68LC302 multi-protocol processor.

The chip includes an Independent Direct Memory Access (IDMA) Controller, Interrupt Controller with Two Modes of Operation, and on-Chip 1152-Byte Dual-Port RAM for handling the data flow. The two independent, full-duplex serial communications controllers (SCCs) support various protocols, from High-Level/Synchronous Data Link Control (HDLC/SDLC), Universal Asynchronous Receiver Transmitter (UART), and Binary Synchronous Communication (BISYNC). The MC68LC302 has been designed specifically for low-power applications and handling multiple protocols.

The inclusion of a static 68000 core, coupled with the low power modes built into the device, makes it ideal for handheld or other low-power applications. The 32 kHz or 4 MHz PLL option greatly reduces the total power budget of the designer’s board, and allows the MC68LC302 to be an effective device in low power systems. The MC68LC302 can then optionally generate a full-frequency clock for use by the rest of the board. During low power modes, the periodic interrupt timer (PIT) allows the device to awaken at regular intervals. In addition, two pins can awaken the device from low power modes.


With high-speed processing moving further out to the edge of the telecom network, the needs of the system designer are changing. More high-performance multi-core devices can be used towards the edge of the network to provide routing, security and analysis, and offload some of the data traffic from the core. Network processors are providing more performance within the same power envelope as previous generations to allow more cost effective use further out in the network, and providing more opportunities to combine processors within the core.