Reflecting the global trend for low power, microcontroller manufacturers are coming under increasing pressure to drive down the power consumption of their MCUs; the current ‘line in the sand’ is 100 μA/MHz.
But why is this becoming so important to OEMs and, more importantly, just how achievable is this in practice? What are IDMs doing to deliver ultra-low-power operation? Choosing a device with low-power features is only part of the story; just as important is how the MCU’s CPU is implemented and architected to deliver ultra-low-power operation.
This article will take a look at this trend, examine recent solutions from Texas Instruments (MSP430FR5720), Freescale (MKL15Z128VLK4-ND, MKL25Z128VLH4-ND), NXP (LPC1100L), Energy Micro (Gecko), Atmel (UC3 L family) and Silicon Labs (SiM3Lxx), and look at existing solutions that may be equally capable of achieving ultra-low-power operation through good design techniques.
The migration path taking OEMs from 8-bit to 32-bit microcontrollers has been forged, to date, on a predominantly mid- to long-term view that posits applications are only getting more sophisticated and will, therefore, at some point need to adopt more powerful architectures.
This argument is commonly simplified to ‘a rising level of complexity at the software level’, much of which is warranted; many of the efficiency gains made over recent years have been possible mainly through more sophisticated algorithms used in industrial control applications. In addition, greater levels of connectivity are now demanded by OEMs, which typically demands complex protocols. Few would argue that more powerful microcontrollers (MCUs) are able to integrate this complexity and connectivity with ease, providing significant benefits without the need for additional discrete devices.
Modern 32-bit architectures, once the domain of microprocessors, now enable a range of highly powerful and capable MCUs, characterized by the deployment of ARM®’s Cortex™-M family of cores in MCUs that can now cost as little as $0.50/each in production volumes. However, since their inception, 32-bit MCUs have faced stark resistance from the industry at large; resistance has systematically been eroded through developments and improvements in the 32-bit offerings. There are many things 32-bit devices can do better than their 8-bit counterparts.
However, the latest and, perhaps, longest standing point of contention is power consumption. It is true that you do not get anything for nothing and some applications are able to accept an overall increase in system power if it enables an overall and commensurate increase in customer value, which in turn can provide a competitive advantage or improved profit margin. However, some applications — and especially those served by low-end MCUs — are not able to accept increased system power and it is here that device manufacturers have focused their efforts for improvements.
The latest angle of attack is to highlight active power, that being the amount of system power drawn while the MCU is actually doing something. Active power is the ‘elephant in the room’ for 32-bit MCUs, as they typically run at higher frequencies than 8-bit devices, predominantly because their RISC instruction cycles are more complex than the 8-bit ‘fetch-execute’ approach.
As a result, engineers are beginning to be presented with 32-bit devices claiming to deliver less than 100 µA/MHz active power consumption. While this undoubtedly delivers overall system power savings, it is still a relative term. Many 32-bit devices run at around 80 MHz, putting active power up to 8 mA and bringing it back into the ballpark of older 8-bit devices. So what other methods are device manufacturers using to minimize the power drawn by 32-bit devices?
It is difficult to differentiate at the core level when using a commoditized piece of IP such as ARM’s Cortex-M family. However, not all device manufacturers have standardized on this architecture for their ultra-low-power offerings. Texas Instruments continues to promote the benefits of its 16-bit series the MSP430, which now features an ultra low power version, codenamed Wolverine (MSP430FR57xx).
The unique feature of this family is its substitution of the conventional embedded Flash memory for the less conventional FRAM (ferroelectric RAM). This, TI claims, lowers the system power significantly when measured against a 32-bit Flash-based device, bringing its active power down below the ‘100 µA/MHz’ industry benchmark. By way of example, the MSP430FR5720 is documented as offering a typical power consumption of 81.4 μA/MHz.
In the ARM camp, both Freescale and NXP now offer devices based on the latest Cortex-M0+ ultra-low-power core, both of which are billed as hitting the sub-100 µA/MHz power point. Both also have low power offerings already in the market.
Freescale was first to market with its Cortex-M0+ parts (thanks to being ARM’s lead design partner for the new architecture) with its Kinetis L family. Hotenda offers a range of Kinetis L devices, including the MKL15Z128VLK4-ND and MKL25Z128VLH4-ND. All the devices in Freescale’s Kinetis L family feature the Cortex-M0+ core running at up to 48 MHz, which integrates a range of clock modes that limit switching activity to different parts of the core, under software control. Proper understanding and use of these clock modes can significantly lower the active power drawn by the device.
NXP, who recently announced its Cortex-M0+ family, already offers a range of MCUs based on the incumbent Cortex-M0 core, including the LPC1100L series. While this family features the older version of the core, it still offers ARM’s inherent power-centric approach to low power processing and integrates a range of features to minimize active power.
For example, the LPC1100L integrates a number of pre-configured but flexible ‘power profiles’, which can modify and control the device’s clocking domains. They are presented as software routines resident in the device’s ROM and this means the profiles can be initiated by a simple API call from within the application code. They aim to deliver the optimal mix of CPU performance, CPU efficiency and active current, delivering the maximum operating frequency across the entire supply voltage range (1.8 V to 3.6 V). The focus of the APIs is to lower the active current while keeping CPU performance up and NXP claims benchmarks have shown as much as a 30% improvement in power consumption by using the power profiles.
Figure 1: NXP’s low power LPC1100L family is based on the older Cortex-M0 core, integrating some excellent low-power techniques.
However, as will be shown next, there are a number of other techniques device manufacturers can adopt in order to lower active power, beyond an optimized core.
While raw processing power is becoming more important in MCU applications, the key attribute of any microcontroller remains its peripheral set. In conventional architectures, the core and its peripherals work together in a ‘handshake’ fashion where data is passed from peripheral to core and back through a peripheral to the larger system.
Although this approach is undoubtedly efficient in terms of response time and throughput — and describes perfectly the original intention of MCUs — it reflects a time when typical applications were less demanding and there was less pressure on engineers to develop power-efficient solutions. Modern 32-bit MCUs now target more demanding applications, while striving to remain ‘low power’, a term that is increasingly overused and under-justified. However, most manufacturers appreciate they are unlikely to achieve design wins with an MCU family that does not fully embrace the need for low power operation and provide innovative techniques to achieve it, beyond the core. An increasingly popular solution is to reduce the need for the core to do anything, based on the premise that the longer the core can remain inactive, the lower the overall power consumption will remain. This theory is being implemented through peripherals that are able to operate autonomously.
As this feature has developed, manufacturers have extended it to allow peripherals to interact with each other while the core remains in a deep sleep mode, even to the extent of modifying their own behavior through flags and registers.
A pioneer in this area is Atmel with its picoPower technology. Atmel’s first 32-bit family to implement picoPower was the UC3 L family, which is based on its proprietary AVR core. It uses a DMA (direct memory access) controller to allow peripherals to pass data to each other over a dedicated and deterministic backplane, making it suitable for real-time applications but without the use of the core.
Another manufacturer to implement autonomous peripherals is Silicon Labs, who has developed the SiM3Lxx ultra low power ARM Cortex-M3 based family, which takes the concept a stage further to introduce the Data Transfer Manager (DTM) — allowing multiple peripherals to be configured and controlled in multiple stages, without any CPU intervention. The DTM augments the more fundamental functions of a standard DMA using a state-driven configuration.
Figure 2: Silicon Labs’ Precision32 family is the company’s first ARM Cortex-M product offering and features autonomous peripherals.
Essentially the objective of autonomous peripherals is to allow the MCU’s core to remain in a deeper sleep state for longer. In many applications, the MCU is reactionary; it is only needed to operate when reacting to external stimulus. Moving the initial processing and decision making to more ‘intelligent’ peripherals that only wake the core when the stimulus meets predetermined parameters, obviates the need for a ‘housekeeping’ loop that wakes the core periodically only to check for possible events. Autonomous peripherals, on the other hand, generate an interrupt when needed, allowing the core to sleep.
One of the first manufacturers to adopt this approach was Energy Micro, using the Cortex-M3 core in its range of ‘ultra low power’ MCUs. The Gecko range implements autonomous peripherals that remain active when the core and main system clock are effectively switched off, relying instead on an independent lower frequency clock source to keep the peripherals active, without the intervention of the core. When enabled with an interrupt request feature, autonomous peripherals are able to wake the core only when it is needed to process data.
Figure 3: Energy Micro was a pioneer in autonomous peripherals and now offers its Gecko family in ever-smaller packages.
Atmel’s picoPower technology also includes this feature, which it actually calls SleepWalking. In essence, it enables peripherals to make ‘decisions’ based on the peripheral’s capabilities; an ADC, for example, can initiate an interrupt if an input exceeds a preconfigured limit.
These features are complementary to the now standard plethora of sleep modes available in modern MCUs, particularly those featuring a 32-bit core. While ARM is responsible for many of these low power modes, it is often necessary for the manufacturer to implement a system-wide solution that takes in to account the impact of putting the core into a sleep mode. Ultimately, it means removing power and/or clock signals from various domains within the core and its sub-systems. Instigating separate clock domains for peripherals is now viewed as ‘standard’, but it is still a relatively new feature, and one that 8-bit devices are less likely to develop due to the reduced need and, perhaps, perceived lifetime of 8-bit devices.
It seems ironic that, for all their efforts to migrate OEMs to higher performance 32-bit MCU architectures, device manufacturers still need to make enormous efforts to enable these devices to remain inactive for as long as possible, while maintaining very low power consumption when they do become active. This dichotomy, however, can only be enabled by the increased power of the devices both at the core level and through ever more sophisticated peripherals. It seems unlikely that this level of design effort will find a return if invested in 8-bit architectures, which means their days really are numbered — whether the industry likes it or not.
Of course, device manufacturers are committed to continuation of supply; many 8-bit devices are used in industrial applications that have many years of commercial life in front of them, manufacturers are unlikely to force customers to move to 32-bit families where no good reason to do so exists.
While the next wave of MCUs will compete at ever-lower active power figures — currently 100 µA/MHz — there is already a wide range of low power solutions in the market ready for volume production, providing engineering teams the confidence that for whatever solution they choose, it is very likely on a roadmap to even lower power consumption.