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Miniaturization is driving microcontrollers into ever-smaller packages with increasing performance. As the controller cores get smaller using advanced silicon manufacturing processes, there is more opportunity to add peripherals and reduce the size of the device. At the same time, power consumption increases from the higher performance, additional peripherals and the increased leakage currents, driving up the thermal requirements.
All of this creates a fine balance of clock speed, voltage and packaging technology to provide the optimum performance for a microcontroller in a miniaturized system. Managing the power in the microcontroller is a key factor in maintaining the system within the thermal envelope without having to use active cooling such as fans that reduce the reliability in embedded systems.
While passive cooling such as heat pipes can be used to transport the heat away from a heatsink to cooling fins, this increases the size of the system and negates the miniaturization of the processing. So the management and handling of the power in the controller is a key element in the miniaturization of the overall system.
The smaller the controllers become, the more focus is on the thermal characteristics of the packaging and the system. Moving to a chip-scale package allows new thermal management techniques to be used such as thermal coatings. This is made more necessary as the silicon die is often made thinner to reduce leakage current and capacitance, but this reduces the thermal reservoir available and potentially makes the die more vulnerable to cracking with thermal imbalances.
The ARPA research agency in the US has a Thermal Management Technologies (TMT) Program that is exploring and optimizing nanostructured materials so that they can be used in thermal management systems. It is working on thermal ground plane (TGP) technology with high-performance heat spreaders that use the two-phase cooling of heat pipes to replace the copper alloy spreaders in conventional systems to boost the cooling without having to change the design of the system.
The program is also looking to enhance air-cooled exchangers by reducing the thermal resistance through the heat sink to the ambient, increasing convection through the system, improving heat sink fin thermal conductivity, optimizing and/or redesigning the complimentary heatsink blower, and increasing the overall system coefficient of performance.
At the same time, the nanothermal interface (NTI) project is looking at new materials and structures that can provide significant reductions in the thermal resistance of the thermal interface layer between the back of an electronic device and the next layer of the package, which could be a spreader or a heatsink.
This is intended to avoid the need for thermal substrates such as ceramic materials, which can be expensive.
There are various techniques that can be implemented in the microcontrollers to keep the power within the thermal envelope of the system. Reducing the voltage of the system reduces power, and the ability to switch off the various blocks in the device when they are not in use helps to reduce the thermal activity. Similarly reducing the clock frequency to match the processing requirements and adding clock gating to switch off peripheral blocks also helps manage the power.
This is shown in NXP's latest microcontroller, the LCP54102, which addresses the power issue with a combination of processors. An ultra-low-power 32-bit ARM 100 MHz Cortex-M0+ core operates with a power consumption of 55 μW/MHz for managing peripherals and monitoring the system, with a larger 100 MHz ARM Cortex-M4 processor for complex algorithm handling. The 3.3 x 3.3 mm chip uses a 90 nm process with 256 KB of flash and 104 KB of SRAM, ADCs, timers and digital interfaces.
Figure 1: NXP's Espresso development board with the LCP54102 microcontroller.
All of this is aimed at reducing the overall power consumption of battery powered sensor fusion applications, as the voltage is automatically adjusted between 0.85 V and 1.35 V to match the different frequency set for each of the processor cores depending on the power profiles. These power profiles are in the ROM with an API to easily manage all the peripherals on the chip and the frequency and sleep modes of the cores, although these can also be adjusted directly. Both the settings and the API are accessible through the Espresso development board. However, the packaging and the system design has to take into account the maximum power dissipation of the device. While the average power may be reduced, and the power used in idle mode is also lower, the peak power has to be accommodated with heatsinks and ways to move the heat away from the core processor.
An example is the wafer-level chip-scale package (CSP) developed by Freescale Semiconductor for its Kinetis KL03 processor that measures just 1.6 x 2.0 mm.
Figure 2: Freescale's chip-scale packaging for the Kinetis KL03 microcontroller.
The KL03 CSP (MKL03Z32CAF4R) reduces board space while integrating features such as a low-power (LP) UART interface, SPI, I²C, analog-to-digital converter (ADC) and an LP timer which supports low-power mode operation without waking up the core alongside ARM's Cortex-M0+ core.
The single-cycle fast I/O access port allows efficient bit banging and software protocol emulation, keeping an 8-bit "look and feel" while keeping the power consumption down, and multiple flexible low-power modes include a new compute clocking option that reduces the dynamic power by placing peripherals in an asynchronous stop mode.
As a result, the Kinetis KL03 CSP consumes 35 percent less PCB area but with 60 percent more GPIO than other devices. This allows designers to dramatically reduce their board size without compromising the performance, feature integration and power consumption of the end product but still highlights the need for good thermal management.
Through the acquisition of Energy Micro, Silicon Labs now has a range of the highly energy-friendly microcontrollers. With a combination of the 32-bit ARM Cortex-M0+ core, innovative low energy techniques, short wake-up time from energy saving modes, and a wide selection of peripherals, the EFM32ZG microcontroller is aimed at low energy designs.
A key element in the microcontroller is the Energy Management Unit (EMU) that manages all the low energy modes (EM) in the microcontrollers. Each energy mode manages if the CPU and the various peripherals are available. The block can also be used to turn off the power to unused SRAM blocks. This links to the Clock Management Unit (CMU) that controls the oscillators and clocks on the chip, turning the clock on and off on an individual basis to all peripheral modules in addition to enable/disable and configure the available oscillators. The high degree of flexibility enables software to minimize energy consumption in any specific application by not wasting power on peripherals and oscillators that are inactive.
Another family of microcontrollers using the ARM Cortex-M0 core is the XMC1000 from Infineon Technologies. This is using a 65 nm manufacturing process to overcome the limitations of today’s 8-bit designs with flash memory scaling from 8 KB to 200 KB. The XMC1200 line features peripherals for LED lighting and human interface designs, and the XMC1300 series addresses the real-time control needs of motor control or digital-power-conversion applications. As the family is aimed at replacing the controller in 8-bit designs and so is packaged in 16 and 38 pin plastic TSSOPs, there are more thermal considerations. These can be tackled with deep sleep modes to shut down the chip when not in use.
The drive to the miniaturization of systems brings challenges in the thermal design and management of microcontroller sub-systems. This can be done with new heat pipe and packaging technologies to compensate for the increased power dissipation, and also with more sophisticated power management techniques. Being able to use the system software to control the clock signals and voltages to individual peripheral blocks as well as the controller core can also help to reduce the power consumption to allow the silicon to operate effectively in existing, or even smaller chip-scale packaging. This helps balance the competing demands of reducing the size of the core and the package with the thermal requirements of the system.