Packaging of microcontrollers plays a key role in the miniaturization of a system. The tradeoff of the choice of peripherals on the die, the pad count and the die size all limit the ability to reduce the size of the microcontroller, but nevertheless help reduce the overall size of the end equipment.
Thermal issues are also important to consider as microcontrollers get smaller in size. With more transistors on a small die, running at higher frequencies, the power dissipation is a key consideration. While reducing the voltage and gating the different peripherals so that unused elements are not consuming power can reduce the overall thermal load, the excess heat generated must then be efficiently removed or the microcontroller will degrade and ultimately fail. This is a key reliability issue that has to be considered in miniaturizing the microcontroller system.
This is where the tradeoff of pins versus size comes in. Additional pins on a package can be used to connect to thermal vias to take excess heat away from the microcontroller and other devices that may be sensitive to elevated temperatures such as a wireless interface.
While the latest chip-scale packaging can reduce the overall footprint of a device with a given functionality, reducing the area taken up by a quarter, the opportunity to integrate more peripherals into a device and have more pins for thermal dissipation may be more important.
The designer also has to be aware of the aim of miniaturization. An ARM 32-bit core, such as the Cortex-M0+ or even the M4, is less than a square millimeter of silicon – the size of the die is determined more by the amount of memory on chip and, vital for the packaging consideration, the peripherals that need to connect to the outside world. The smallest M0 devices, such as Freescale’s Kinetis KL02
, can be as small as 1.9 x 2.0 mm in a chip-scale package that is barely larger than the die itself. At less than 4 square millimeters, this occupies twenty-five percent less PCB area than ball grid array or LGA packages but provides sixty percent more GPIO with up to twenty-eight lines. This move, almost 'silicon dust', allows designers to dramatically reduce their board size without compromising the performance, feature integration and power consumption of the end products.
Figure 1: The Kinetis KL02 family in chip-scale packaging provides a full microcontroller in a few square millimeters.
Power consumption and thermal considerations are key at this size, and there are many things that can be done on the chip to reduce overall power dissipation and allow for a smaller package. The core runs at 48 MHz, helping to keep the power down over the whole -40°C to +105°C temperature range and allows the devices to be used in as many different environments as possible. There are also multiple low-power modes such as a new compute mode that reduces dynamic power by placing peripherals in an asynchronous stop mode. The Low-Power UART (LPUART), SPI, I²C, data converters, low-power timer and DMA engine all support a low-power mode operation where they operate without waking up the core.
However, this does not necessarily reflect the actual use of silicon. Making many different versions of a microcontroller with a wide range of peripherals and memory options is actually expensive if separate masks are required. Instead, a single design with a superset of functions is implemented and manufactured, and only a specific set of features connected. This allows the silicon vendor to provide a wide range of products while minimizing the manufacturing costs and benefiting from economies of scale.
The next stage of development has been to create a more flexible I/O configuration. Just as an internal bus matrix connects the peripherals, (as in the Atmel 4S family
) so vendors are also introducing designs with a matrix that connects the I/O pins. This allows any peripheral to connect to any I/O pin, providing more flexibility for the vendor to deliver a family of pin-compatible devices where the same I/Os are always in the same place. As there is silicon to spare, this helps the system designer have a design with scalable performance without impacting on the overall size.
All this means that the packaging technology is the key to the miniaturization of the microcontroller. Atmel has developed the SAM G51
series of Flash microcontrollers that is also based on the M4 core with floating point support. This also operates at a maximum speed of 48 MHz and features up to 256 Kbytes of Flash and up to 64 Kbytes of SRAM. The peripheral set includes one USART, two UARTs, two TWIs, one high-speed TWI, up to two SPIs, one three-channel general-purpose 16-bit timer, one RTT and one 8-channel, 12-bit ADC, greatly driving up the pin count requirements.
Figure 2: The Atmel SAM G51 family of microcontrollers showing the range of package options.
This peripheral set allows the SAM G51
series to target a wide range of applications including
consumer, industrial control, and PC peripherals with just two package types – a 49-ball WLCSP chip-scale package or a 100-lead LQFP package.
At the same time, Atmel's SAM4S series is also based on the ARM Cortex-M4 processor core. It operates at higher maximum speed of 120 MHz and features up to 2048 Kbytes of Flash, with optional dual-bank implementation and cache memory, and up to 160 Kbytes of SRAM. The peripheral set includes a full-speed USB device port with embedded transceiver, a high-speed MCI for SDIO/SD/MMC, an external Bus interface with memory controller, two USARTs, two UARTs, two TWIs, three SPIs, one I²S, as well as one PWM timer, two three-channel general-purpose 16-bit timers (with stepper motor and quadrature decoder logic support), one RTC, one 12-bit ADC, one 12-bit DAC and one analog comparator.
All of this brings even greater demands on the packaging and the pin count. The family has up to seventy-nine I/O lines with external interrupt capability (edge or level sensitivity), debouncing, glitch filtering and on-die series resistor termination, as well as three 32-bit Parallel Input/Output Controllers.
This leads to a range of packages, from 100 leads down to 48 leads, but using the more traditional technologies:
- LQFP, 14 x 14 mm, pitch 0.5 mm
- TFBGA, 9 x 9 mm, pitch 0.8 mm
- VFBGA, 7 x 7 mm, pitch 0.65 mm
- LQFP, 10 x 10 mm, pitch 0.5 mm
- QFN, 9 x 9 mm, pitch 0.5 mm
- WLCSP, 4.42 x 3.42 mm, pitch 0.4 mm (SAM4S16/S8)
- WLCSP, 3.32 x 3.32 mm, pitch 0.4 mm (SAM4S4/S2)
Figure 3: The Atmel SAM4S family has a much wider range of peripheral options leading to larger packages.
- LQFP, 7 x 7 mm, pitch 0.5 mm
- QFN, 7 x 7 mm, pitch 0.5 mm
New packaging technologies that stack die on top of each other in the same package also help to reduce the overall footprint. Instead of having a separate memory chip alongside the microcontroller, the microcontroller die is mounted on top of a memory die or large FPGA in one package. This approach, commonly called 2.5D, requires a silicon interposer and through silicon vias (TSVs) which is a relatively new technology that is now maturing and becoming more common. This is used in high-end devices that need larger amounts of memory that cannot be cost effectively integrated on a single die.
Full 3D packaging sees multiple die stacked directly on top of each other; perhaps with I/O pads on the edges to allow interconnect between the different devices. While this has been a long-term aim of miniaturization, combining all the elements on a printed circuit board from the microcontroller to memory and wireless interface into one packaged device, it has yet to overcome a number of cost, reliability and thermal issues.
The wide range of microcontrollers from multiple vendors hides a strategy in the miniaturization of such devices. The range of packaging in different families from one vendor, all around the same core, demonstrates the complex tradeoff between footprint, peripheral mix, power, and system size. Further down the performance curve, 32-bit controllers with complex peripherals are now little more than a couple of square millimeters, becoming 'silicon dust' that permeates the Internet of Things.