Any logic designer will tell you, discrete logic works well, but is never really the ideal solution. Unless all you need is a single gate or inverter, building logic functions from discrete logic chips can take a lot of devices, board space, and power. This is especially true as higher-level functional blocks are forged with primitive logic elements from the ground up.
Ultra-low-cost evaluation and development kits are a good way to explore a technology that may be new to you without much risk or time. PLD technology is a prime example.
Lattice Semiconductor is one of the PLD, CPLD, and FPGA providers who offer a low cost development kit that supports the MACHXO2, one of their family members. This article takes a look at the capabilities and features of the MACHXO2 family and the new MACHXO2 PICO development kit. It peeks “under the hood” and lets you know what to expect if you decide that there is an opportunity to use programmable logic in your path. All parts, development kits, boards, training materials, and data sheets referenced here can be found online on Hotenda’s website.
Programmable Logic Devices have been around for a long time and have earned their way into our boards and systems. Early simple, sum-of-products, fusible-link technology has given way to ASIC-like densities and in-system Flash-based re-programmability. I/O cells have improved to provide higher speed interfaces, differential interfaces, high-drive and sink pins, as well as offering dynamic bi-directional control. Very useful on-chip resources include oscillators, PLLS, regulators, charge pumps, and other system functions.
One key advance is function libraries available for today’s PLDs, CPLDs, and FPGAs that provide canned function-block solutions to simple and complex sub-systems. While some IP is bought or licensed, device makers provide many free IP blocks to entice us into using their parts. These include UARTs, I²C and SPI interfaces, memory controllers and more.
Tools make a difference, as well, and here, most PLD makers have their own or receive support from third parties. Tools can be free or expensive. It is not always true that you get what you pay for. In many cases, free or low-cost tools are as good as the store-bought flavors or better. This is especially true when it comes to taking advantage of specific CPLD and FPGA architectures.
The inner architecture
Inside CPLDs and FPGAs are a variety of architectures and resources. Sometimes there are limitations such as routing constraints. Other times, there are functional constraints, such as gates not wide enough to handle the number of inputs in a single stage. The volatility of the programmed function is important, too.
However, volatile and non-volatile flavors of CPLDs and FPGAs are available, and both have advantages and disadvantages. Volatile parts can be very dense and fast, but need to be loaded with their program when power is first applied. From a design point of view, this is simple since all the work is done. We merely bolt on a special serial Flash to the FPGA, and when power is first applied, it clocks into the part.
There are two downsides to this approach. One downside is that the parts are not instant-on. This means that all other circuits have to wait until the programmable logic device is loaded and ready. This may include keeping a microprocessor in standby until ready. The second downside is the need for an additional chip that holds the program. This adds cost, takes up space, and needs to be programmed itself. As an alternative, you could choose not to use the CPLD or FPGA in the processor’s decode path and let the processor clock the code into the CPLD or FPGA. A third possible downside is the lack of protection or security of your design since the bit-stream that programs your part is exposed. You need to be aware of these issues before committing to an architecture.
Instant-on parts use Flash or EEPROM non-volatile memory to hold the functionality inside the device when power is lost. Upon power up these parts are ready to go – no wait or hold time. This means they can be used in the path of a processor for decode purposes right away. This also means that prying eyes cannot easily gain access to your design code.
Look it up!
Another difference in architecture is the way the logic is implemented inside the CPLD or FPGA. Very fine granularity of gates enables highly dense parts to be quite flexible. Every digital logic function can be built from the ground up using only NAND or NOR gates. While flexible and fast, routing limitations may make some functions hard to implement. Also, unless ‘hard coded’ to map to specific gates, the timing characteristics can vary greatly depending on how your tools place and route.
Functional blocks or macro cells represent another approach to encapsulating logic inside a CPLD or FPGA. Function blocks bigger than gates are implemented here. These can be as simple as a few flip-flops and gates, all the way up to multiple input and output cells that look like older style PALs, such as the 22V10.
Another architecture you will see is the Look Up Table (LUT) approach. Here, SRAM-based cells are merely addressed by the logic inputs. On the plus side, small logic functions can occur very quickly since the outputs are as fast as the access time of the SRAM. On the down side, each bit added to the width doubles the size of the memory array needed. This means that very wide functions, such as 20-bit AND gates, will typically need more than one level of logic, which will increase propagation delay and response time.
Nevertheless, all these architectures have their place and are available today from various manufacturers. Now that you understand the differences, let us take a look at Lattice Semiconductor’s parts.
Inside the MACHXO2
The MACHXO2 is a Flash-based, non-volatile, instant-on LUT-based family of CPLDs with embedded hard-wired functions available. The family includes six main members, with densities from 256 to 6864 LUTs and from 19 to 335 I/O, and in packages ranging from 25-pin 2.5 x 2.5 mm WLCSP ball up to 484 ball FPBGA at 23 x 23 mm.
Three flavors of power functionality are available with the HC parts peaking at 48 mW, the HE at around 5 mW, and the low-power ZE, which peaks out at 0.23 watts. Refer to the data sheets for specifics.
I/O is routed to and from the internal routing pool and logic blocks through input and output ‘gearboxes’. These are I/O structures that allow dynamic control of the direction, tri-state modes, and inversion pairs (for differential), as well as pipelined and paralleled flip-flops for input and output latching. Also included are programmable pull-up or pull-down resistors, on-chip differential termination, Schmidt trigger inputs, LVDS, LVCMOS, and several other I/O standards at 3.3, 2.5, 1.8, and 1.2 volt levels.
Note that all programmable logic has granularities, and Lattice is no exception. Looking at it hierarchically from the top down, the MACHXO2 family architecture is a structured array consisting of a matrix of Programmable Function Units (PFUs) surrounded by routing resources, system and user SRAM, system and user Flash, programmable I/O, and system resources (see Figure 1).
Figure 1: The top-level architecture of the MACHXO2 uses an array of Programmable Function Units (PFUs) as the core logic element. User RAM, Flash, and hard-wired blocks like I²C and SPI master/slave controllers are also available at this level. (Courtesy of Lattice Semiconductor.)
Drilling deeper into the hierarchy, a PFU consists of four slices with cascaded carry-ins and carry-outs (see Figure 2). This is useful for counter chains and arithmetic blocks. PFUs have access to the routing pool as inputs and as outputs. As such, signals from a local PFU or Slice can be fed back to create sequencers and state machines.
Figure 2: Inside each PFU are four sub-elements called Slices. The routing pool sends inputs and accepts outputs of the PFU’s I/O. (Courtesy of Lattice Semiconductor.)
Drilling even deeper, a Slice contains two 4-input LUTs with latched or real-time outputs (see Figure 3). Multiplexing control, output selection, clocking source, carries, and more allow the Slice to be a very flexible logic unit in a relatively small area.
Figure 3: At the lower part of the hierarchy are the Slices, which contain two LUT blocks with input and output routing, carry cascading, and multiplex control. (Courtesy of Lattice Semiconductor.)
Eight primary clocks can be generated and distributed around the internals. Clock sources can come from input pads, the internal PLL, or divider and gating logic inside the chip. Two of the eight are switchable on the fly, which is useful for FSK modulation. There are also eight, high fan-out drive lines available throughout the array. This eliminates having to make clock trees and suffer additive delays.
The MACHXO2 family has on-chip PLLs to enable synthesizing frequencies referenced from input pads or from internal logic. It takes advantage of a 16-bit fractional-N synthesis technique that allows these blocks to generate output clocks that are non-integer multiples of the input frequencies. There is also an on-chip oscillator that can run from 2 to 133 MHz. Clock signals can go to the internal clock tree, or to the PLL as a reference frequency.
There are also single-port, dual-port, FIFO, and ROM memory blocks available for the design. ROM blocks can control clocked sequencer-style state machines or hold code for Lattice’s logic-based MCU. SRAM, dual-port, and FIFO RAM can enable designers to create elastic buffers for serial data streams, for example.
Speaking of serial data, the MACHXO2 family also has hard-wired support for I²C (Master or Slave), SPI (Master or Slave), and UARTs. Every device also has a JTAG port for programming and configuring the devices.
Tools of the trade
This is just an overview of the inner workings of the MACHXO2 family. As you can see, there is much thought and engineering effort put into making these things as useful as possible. Fortunately, we do not need to study these parts to such an extreme level. Instead, we can take advantage of the tools to allocate the resources we need in an efficient and effective way. Additionally, Lattice has some remarkably high-power free tools available.
The flagship toolset is the Lattice Diamond program (see Figure 4) which replaces their older ISPLever software. It is able to import older ISPLever files, so it does not leave you in the cold.
Figure 4: The Free Diamond tool set from Lattice is a complete design environment that allows blended schematic and HDL inputs and performs simulation, place and route, and timing analysis. It even supports programming. (Courtesy of Lattice Semiconductor.)
Detailed evaluations of the software is beyond the scope of this article, but suffice it to say this toolset handles blended VHDL, Verilog, and schematic entry and performs synthesis, simulation, timing analysis, place and route, and even programming of the parts. It is free, but you have to register to get a node-locked license.
Diamond supports six of the company’s CPLD and FPGA families. Subscription licenses are available for full support, which also includes third party tools. All the software can be downloaded from their website. There are installation guides, tutorials, training materials, and application examples. The help is rather extensive and detailed. Note that this is a full-blown design environment, so expect to devote some time to mastering its intricacies.
The Pico Development/Evaluation kit
I ordered the Pico development/evaluation kit and set up a workspace for it. It arrived quickly in a single box that contained the circuit board, a battery, a USB cable, and a Quick Start guide. This small board contains one of the LCMXO2-1200 family members, a middle-of-the-road part with 1280 LUTs inside.
The LCMXO2-256 is the smallest family member with 256 LUTS; the LCMXO2-640 contains 640 LUTS. Family members grow to include the largest part, the LCMXO2-7000 with 6864 LUTs – dense for instant-on high-speed (~7 nsec) CPLDs.
The resources available to play with on the development board include a small 4-digit 7-segment LCD, four PCB capacitive touch buttons, a pushbutton, an I²C temperature sensor; and a 1-Mbit SPI Flash (see Figure 5). A 2 x 16 GPIO 100 mil-spaced DIN header provide access to the chip’s I/O. A USB cable allows communications and program control using a USB-to-UART converter chip.
Figure 5: The single-board development kit runs a demo, which uses the Lattice Mico8 embedded controller inside the MACHXO2. The USB port doubles as a JTAG port so you can upload new firmware and logic code (Courtesy of Lattice Semiconductor).
Lattice has an integrated 8-bit LatticeMico8 controller block that can live with the FCBs inside the chip (see Figure 6). The Pico SoC Demo is pre-programmed inside the board. The source code is provided on the website and can be loaded into the Diamond design software. As a starting point, it can be modified for your designs as well. If you need more space, the designs can migrate to larger parts.
Figure 6: The MACHXO2s are really are little SoCs, with embedded control, peripherals, busses, and logic. (Courtesy of Lattice Semiconductor.)
Reference designs for the MACHXO2 family include the LCD controller used on this board, the Serial Control Link, fast-page-mode DRAM control, and – especially nice – a Flash interface controller with wear leveling.
Communications are routed through a terminal program like HyperTerminal since the USB port maps to a COM port using a virtual COM driver. Links on the website let me download and install the drivers and the Quick Start guide clearly indicated the COM parameters to set.
With my COM parameters set up I was able to run HyperTerminal and get the command line interpreter interface screen and interact with the chip and program. Single-letter commands kick off the programmed sequences programmed inside the MACHXO2 part through the UART control block (see Figure 7).
Figure 7: The preprogrammed application let me measure the current using the Delta Sigma converter inside the logic arrays. The little Mico8 embedded controller even ran the applications without USB connected.
An on-board coin battery is provided as an alternative power source. In addition, this development kit has an interesting current measurement app. A Delta Sigma A/D converter implemented in the reference design measures and logs data such as power and temperature into the SPI Flash. Data can be logged, displayed, or cleared using the SPI control blocks (see Figure 7).
I was able to exercise all the functional tests provided in the evaluation part of the software and link this board to the Diamond development software. The functional tests are simple, but are a good example of how to use these parts to implement functions like UART, I²C, SPI, LCD, how to measure the power and current, and so on. These and other applications on Lattice’s website are a good way to get up to speed quickly, and test to see whether your design can benefit from the canned routines. If not, it is still a good starting point, especially since source code is provided for all the examples.
In addition, the schematic¹ for the Pico development kit is also provided in the User’s Guide and as a download from Lattice. This shows the USB to 3.3 V regulators as well 1.2 V core supply. Sense resistors of 1 Ω/1 percent are used to measure the core current and the I/O current. The complete bill of materials is also provided.
Any new technology or the first-time use of an unfamiliar tool or part may seem daunting at first. Fortunately, device makers have bellied up to bar to provide low-cost, low-risk, informative and educational tools, and development kits that get us up to speed quickly and show us what their parts can do. Training Modules can help too. If there is programmable logic in your future, then definitely check out Lattice at Hotenda.
- Pico development kit Schematic