Clocks and clock oscillators (also called clock generators) are a part of nearly every circuit, and most systems have more than one in their design. In fact, it's not unusual to have four, six, or more in a design, supporting internal circuitry as well as external I/O and interfaces. They establish the final carrier setting(s) or re-establish and synchronize to a received-signal carrier. In addition, many systems require the ability to change or shift the clock to accommodate tuning requirements for more than a single end-application situation.
Clocks offer a wide span of functionality and features in serving diverse applications, but also suffer considerable nomenclature and feature confusion with overlapping terms such as clock, oscillator, generator, and synthesizer, among others.
Fixed-frequency clocks are used for pacing processors, memories, and other peripherals. A series of similar products in the same family may need different clock frequencies to support a variety of speed options or functions. These fixed-frequency clocks may also serve as basic timing references in wired and wireless links. Some clocks’ components include a crystal or other timing source which they use to produce their output; others require the user to supply an external crystal.
Some fixed-frequency devices are programmable so the same device can be used across more than a single BOM (bill of materials) to simplify inventory, but even “programmable” devices offer the potential for misunderstanding. They may be one-time programmable at their vendor, one-time programmable on the OEM production line, pin-strap programmable on the circuit board, or software programmable and even reprogrammable “on the fly”. Also, there are programmable clocks which can be reprogrammed a limited number of times, with a frequency which can even be changed a few times to accommodate different production and application demands. To add to the potential complexity, some clock oscillators provide multiple, simultaneous independent outputs, so a single crystal and device can provide the multiple clocks that most systems require.
Further, there are synthesizers which use a single crystal or master clock to generate an arbitrary frequency output within a specified range. As with basic clock oscillators, some synthesizers are fixed once set, others are dynamically settable to provide any frequency (usually a carrier) in a specified spectrum as needed.
In wireless systems, there are two basic groups of clocks: those fixed frequency for setting basic timing on a channel, such as a point-to-point dedicated link, and clocks whose frequency can be shifted as needed to support different channels, such as frequency hopping on a Wi-Fi link.
Given all the clock options, it can be a challenge to decide which basic clock approach is suitable. However, the process can be simplified by concentrating on primary specifications, as not all clock configuration options have comparable specifications. Only devices which meet these top-tier requirements can be considered in various configurations. As always, there are trade-offs in performance to be assessed against weighting of performance attributes.
The most critical speciation is maximum nominal-frequency capability of the clock, which for most wireless applications will span a few hundred MHz to the GHz range. For programmable devices, both the maximum and minimum values are critical; clock ICs generally have a 10:1 or 5:1 max/min span.
Another important specification is initial-frequency error (tolerance) at a given setting, expressed in percentage, Hz, or parts per million. This number may vary depending on the nominal frequency if the clock is not a fixed-frequency device.
All oscillators are subject to drift. If the device contains an internal crystal, or it uses analog circuitry to condition and scale an external crystal, it will undergo some drift with temperature; if it is an all-digital device, drift will be less although there will still be some as thresholds and timing of the logic gates will shift slightly. The temperature coefficient for high-performance oscillators is usually expressed in ppm/⁰C, with values ranging from around ten to several hundred. The maximum acceptable value depends on the application, of course.
For oscillators whose frequency is dynamically switched during use, rather than changed only on initial power up via user-initiated tuning or mode switching, a critical parameter is settling time to the new frequency. Depending on the architecture of the oscillator, this can be almost instantaneous for a synthesizer or PLL-based design, or a relatively substantial period. Even if the core circuitry slews with no discontinuity (as some architectures do), there may be a settling time issue if the associated output buffer amplifier or driver must swing over a large range. Usually, small frequency changes are not challenging, but a wide change may have a longer settling time; in reality, there are few applications where the oscillator must quickly transition over its full range.
Drift is also a consideration in many situations. Clocks with an internal crystal exhibit both short- and long-term drift due to aging of the crystal, although these terms may have different definitions with each vendor. Some define “short-term” as one year and “long-term” as five, ten, or even twenty years. Finally, issues of power consumption and package size factor into the decision, but these are usually of secondary importance compared to the basic performance specifications. In general, lower-power devices have inferior specifications than ones which dissipate more power, but this is an area where advances in processes, design, and test mean that the trade-offs are in flux.
Jitter: the most challenging issue for many reasons
Among the most-critical parameters which engineers must assess when deciding among oscillator options, jitter is the most difficult to characterize and match to the application. In the time domain, jitter appears as minute variations from the “perfect” output (Figure 1); in the frequency domain, it appears as phase/frequency variations (noise) and broadening of the single-frequency signal spectrum (Figure 2). Both perspectives are equally valid ways of looking at the same physical phenomena, and which is the better perspective depends on the situation, applicable standards, and system-performance requirements.
Figure 1: In the time domain, the theoretically “perfect” clock signal (top) shows minute back-and-forth variations (bottom) which is defined as jitter. (Courtesy of IDT)
Figure 2: In the equally legitimate alternative view of the frequency domain, the perfect single-frequency spike (top) becomes a spreading of the frequency components and associated energy (bottom). [Courtesy of IDT]
Jitter is a complex subject and often challenging to quantify for several reasons. It is usually relatively small, yet still a significant factor with respect to the system performance; it has many contributing sources including internal circuit noise, externally-sourced noise, component thermal noise, component imperfections, and thermally-induced mechanical variations. As a probabilistic characteristic, there is no single correct or easy way to define it; among the many definitions in use are peak, rms, average, short-term variation, and long-term average, among many others. Jitter also can appear as non-harmonically related frequency spurs on the output, at some distance from the fundamental frequency (Figure 3a and 3b).
Figure 3a and 3b: Jitter-related spurs are unwanted frequency components which are not harmonically related to the fundamental; the upper trace is a log-log phase noise plot showing spur-free jitter in the frequency domain for a 1066 MHz clock; the lower trace is the same clock but with a 30 dB spur 30 MHz offset from the fundamental frequency.
The effect of jitter can range from errors in A/D sampling and D/A conversion times, “noise” on a signal, increased BER (bit-error rate), increased inter-symbol interference, and many other manifestations. Often the visible impact of clock jitter is elsewhere in the system, such as reduced tolerance to unavoidable channel noise, which occurs as the sampling window shrinks and the ISI eye-pattern closes. The link between jitter and the overall system performance is sometimes hard to judge, and is often complicated by additional jitter that the non-clock parts of the circuit add to the clock signal itself. Oscillator jitter also establishes the phase noise floor, measured in dBc/Hz, a figure of merit (FOM) which is important to applications such as high-performance receiver channels or radar systems.
When matching clock-generator jitter specifications to the application, it’s best to look at what standard (if any) the industry has set for that application (such as IEEE 802.11x), read up on application notes relevant to the application, and carefully study the datasheet along with its test conditions and footnotes.
Examples show diverse offerings
Two clock oscillator/generator IC families show how this basic function has evolved into very different components. The Silicon Labs Si5xx portfolio is well suited for applications ranging from networking equipment, base stations, storage-area networks and broadcast video systems to single-board computers for datacom and telecom. Available in frequencies from 100 KHz to 1.4 GHz, these single, dual, and quad I2C programmable frequency parts feature low-jitter operation. For example, the Si535 provides 0.19 ps RMS type of phase jitter, increasing design margin and system-level performance. Unlike a traditional XO, where a different crystal is required for each output frequency, the Si535 uses one fixed crystal to provide a wide range of output frequencies. This IC-based approach allows the crystal resonator to provide exceptional frequency stability and reliability. In addition, DSPLL clock synthesis provides superior supply noise rejection, simplifying the task of generating low-jitter clocks in the noisy environments typically found in communication systems.
Similarly, the supplier’s Si534 is a quad-frequency crystal oscillator which can provide a single output at any frequency from 10 to 945 MHz and at select frequencies to 1400 MHz (Figure 4). It targets general wireless and wired links, and is configured by the vendor for a wide variety of user specifications including frequency, supply voltage (3.3, 2.5, and 1.8 V), output format (CMOS, LVPECL, LVDS, and CML), and temperature stability; note that specifications including jitter will vary depending on these settings. In this case the user can select which of the four available frequencies (factory set to user order) should appear at the output of this device via two control pins on the package of the small (5 × 7 mm) 8-lead device including the internal crystal.
Figure 4: This Silicon Labs XO includes an integral crystal; it is shipped by the vendor programmed with four output frequencies chosen by the customer, who can then invoke any one of the four at any time via two control lines.
Typical initial accuracy is ±1.5 ppm at 25⁰C, while first-year drift is ±3 ppm and drift over 20 years is said to be ±10 ppm maximum. The vendor provides many jitter specifications, among them are phase jitter (rms) for output frequencies above 500 MHz of 0.25 psec (typical) and 0.40 psec (maximum), and typical output-phase noise at 622.08 MHz of –146 dBc/Hz (with LVPECL output). Settling time when switching among the four possible clock outputs is 20 msec maximum.
Also noteworthy is the Peregrine Semiconductor PE33241 which targets wireless local loops (WLL); RF frequency generation; L, S and C-band synthesizers; and clock recovery in communication systems, mobile terminals, telemetry, radar, and portable radios (Figure 5). This integer-N phase-lock loop (PLL) frequency synthesizer for low-phase-noise applications can reach 5 GHz using a 10/11 prescaler modulus and 4 GHz with a 5/6 prescaler modulus (the latter modulus choice offers somewhat better specifications). The counter values which establish the output frequencies are programmable by user, either via its serial interface or direct hard-wired configuration. The phase noise floor FOM is -230 dBc/Hz for this 48-lead 7 × 7 mm QFN device.
Figure 5: The PE33241 from Peregrine Semiconductor provides user-selectable outputs to 4 or 5 GHz depending on the modulus pair selected; the extremely low-phase-noise floor FOM is -230 dBc/Hz, making it a good fit with radar, telemetry, and advanced-mobile-radio systems.
The frequency range and high performance of this IC mean that evaluating and properly programming it in a given application can be difficult. For this reason, the vendor offers an evaluation board with USB interface (designated EK33241-13) to demonstrate optimal phase noise performance when using an external, stable low-noise reference source (Figure 6). At these GHz frequencies, the ubiquitous FR-4 PC-board material is not suitable, so the evaluation board consists of a four-layer stack with two outer layers of Rogers 4350B (ε r = 3.48) and two inner layers of FR406 (ε r = 4.80) material. The 12-mil (0.30 mm) thick inner layers provide ground planes for the RF transmission lines, for a total board thickness of 62 mils (1.57 mm).
Figure 6: Devices which provide low-noise, high-performance specifications into the GHz spectrum are challenging to evaluate and integrate into the overall system design, so Peregrine provides a USB-compatible evaluation board to facilitate the task.
Clock oscillators are the “heartbeats” of a system’s various functional blocks, and their capabilities and imperfections are among the ultimate factors in establishing maximum achievable performance. Some functions only need a fixed-frequency clock while others require one which is fixed but selectable among several choices (with selection done at the vendor, the OEM, or even in the field) or even fully adjustable. Critical parameters begin with frequency accuracy and range, and extend to drift, settling time, and jitter. Jitter has many causes and can legitimately be judged and measured in many ways, and is thus the most difficult factor to assess, understand, and relate to total system performance.
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