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PowerPSoC Firmware Design Guidelines

Cypress' PowerPSoC offers a flexible way to implement a wide range of HB LED controllers. This article provides a detailed introduction to the process.

PowerPSoC® introduces a new standard of design for power management systems for LED lighting solutions and other high power applications. This device integrates four channels of constant current drivers with the powerful PSoC® core. This article introduces PowerPSoC and compares the traditional and PowerPSoC methods of designing such controllers. This is followed by a detailed description of how to create a functional design which examines the design aspects of a constant current driver based on PowerPSoC, using preconfigured user modules and firmware.

Cypress' PSoC family of devices is well established in programmable mixed-signal, microcontroller-based devices. The traditional method of implementing power management systems (for example, high brightness LED lighting systems) involves using a similar, system-onchip to interface with high power discrete devices such as constant current drivers and MOSFET switches.

In PowerPSoC, the classic PSoC core is combined with high performance power electronics. The result is an integrated, intelligent power electronics solution in a single QFN package. The intent of PowerPSoC is to significantly reduce the cost, part count, and board space of implementing power management systems while retaining performance. This family of devices (CY8CLED04D01) combines up to four independent channels of constant current drivers. These drivers feature hysteretic controllers with the Programmable System-on-Chip™ containing an 8-bit microcontroller, configurable digital and analog peripherals, and embedded flash memory.

PowerPSoC is designed to operate at voltages from 7 V to 32 V, drive up to 1 A of current using internal MOSFET switches, and drive over 1 A with external MOSFETs. For added flexibility, PowerPSoC supports the commonly used power management topologies such as buck, boost, and buck-boost to meet the variety of application requirements. The control loop formed by the internal current sense amplifiers and hysteretic controllers (featuring DACs and high speed comparators) allow a maximum switching frequency of 2 MHz. Hardware modulators − including the Cypress patented PrISM (Precision Illumination Signal Modulation) − interface with the constant current driver channels, and enable the modulation of high brightness LEDs.

There are additional standalone DACs and high-speed comparators that, with the trip capability of the hysteretic controller, provide independent protection to the system and device in case of abnormal conditions, such as over current, overtemperature, and voltage. PowerPSoC also features an internal auxiliary regulator that powers the PSoC core from the high voltage input, and can power other ICs requiring a 5 V supply in the system.

The PSoC core present in PowerPSoC is the same powerful and flexible device that is present in the Cypress PSoC family of devices. Apart from the 8-bit MCU and embedded flash, there are programmable analog blocks that can implement ADCs, DACs, amplifiers, and filters, as well as programmable digital blocks that can implement counters, timers, modulators, UARTs, SPI interfaces, and an I2C hardware module. These provide the capability to perform intelligent microcontroller functions and to interface with external sensors for temperature, ambient light, and more. The presence of communication blocks allows this device to provide standard lighting communication interfaces such as DMX512 and DALI.

PowerPSoC also features the capability to interface with touch sensitive buttons using Cypress' proven CapSense® technology. For more information on PowerPSoC architecture and the various blocks, refer to the device datasheet and technical reference manual.

This article addresses the new standard for designing a power electronics solution to drive high brightness LEDs using PowerPSoC. A parallel is drawn between the traditional method of using multiple ICs and discrete components, and the new method of implementing a power controller, using software and firmware tools in a single integrated device. This article also describes the method for configuring an intelligent power electronics solution for high brightness LEDs, using Cypress software tools to illustrate the simplicity of design at PowerPSoC. A sample firmware project is included as an example of the implementation described.

Switching regulator topologies

High brightness LEDs are rated for output luminosity according to the current driven through them. This creates the need for a constant current driver that performs the task of regulating the current through the LEDs. A switching regulator offers some advantages over a linear regulator. The switching regulator offers higher efficiency, flexibility to use lower input than output voltages, and lower cost. These advantages contribute to its popularity. PowerPSoC is designed with the idea of implementing switching regulators, specifically the buck, boost, and buck-boost topologies.

There are two scenarios for switching regulators. When the input voltage is higher than the output load voltage, the topology used is called a buck regulator. Figure 1 shows the simple schematic of a buck regulator. The main components of this design are the inductor and the switch. The switch is turned ON and OFF by a control loop, according to the amount of current needed through the load. When the switch is ON, the inductor undergoes an energy storage process. When it is turned OFF, the energy stored in the inductor is discharged into the load. The circuit, at this time, is completed by the Schottky diode which turns on during the OFF time.

Figure 1: Buck regulator.

Figure 2 shows the load current waveform when the switch is ON. The current ramp is proportional to the voltage across the inductor, and inversely proportional to the inductance.

Figure 2: ON time.

Figure 3 shows the load current waveform when the switch is OFF. From the equations in these figures, it is evident that the ON and OFF times can be changed by varying the input voltage, output load voltage, and inductance. This changes the current ramp di/dt and that implies a change in the ON/OFF time if the current is the same. The switch's duty cycle D (ON time divided by period) essentially depends on the ratio of the output to the input voltage (Vo/Vin).

Figure 4 is a snapshot of the waveforms of a buck regulator circuit with hysteretic control. The waveform shows the load current. This is essentially a combination of the current waveforms shown in Figure 2 and Figure 3. The current rises to a peak at the end of the ON time, and drops to a trough at the end of the OFF time. This peak-to-peak limit is called the "ripple," and is usually expressed as a percentage of Iavg. This topology is particularly suited for driving LEDs that need a constant current to control intensity.

Figure 3: OFF time.

Figure 4: Buck regulator waveform.

When the input voltage is lower than the required load output voltage, the topology used is called a boost topology. Figure 5 shows a schematic of a simple boost circuit. The important parts of the circuit are the switch and the inductor. The main difference in this circuit is caused by the position of the switch with respect to the inductor. The switch is turned ON and OFF by a control loop according to the required current and load voltage.

Figure 5: Boost topology.

Similar to the buck circuit, the inductor is charged when the switch is ON and discharged when the switch is OFF. However, when the switch is OFF, the total voltage presented to the output is the combination of the input supply voltage and the voltage across the inductor that is held by virtue of the energy stored in it. This presents an output voltage that is higher than the input voltage, or in essence, the circuit has "boosted" the voltage. The diode is present in this case to prevent the output voltage from decreasing when the switch is OFF.

When the switch turns ON after a previous OFF period, the capacitor across the load holds the output voltage for the duration until the switch turns OFF again. However, the discharge of the capacitor causes the current through the load to start decreasing.

The boost topology is most popular in mobile applications that can be powered only by a low voltage source such as a battery. For high brightness LED applications, the buck topology is usually more popular, because the application is typically non-mobile and a sufficient voltage supply is usually available. Additionally, the boost topology results in an input current with a large ripple, which must be countered by a bypass capacitor.

For these reasons, this article concentrates on the buck topology and shows how this scheme is achieved effectively using PowerPSoC. However, it must be noted that PowerPSoC is flexible enough to also implement the boost and buck-boost topologies if required. For designing a boost topology, refer to the application note AN61668 – "Boost Topology for HB-LEDs." For designing a buck-boost topology, refer to the application note AN60142 — "Floating Load Buck- Boost Topology for HB-LEDs."

Design platform overview

Traditional method

The traditional method of implementing a constant current driver uses a microcontroller which generates the PWM signals based on firmware control. These signals are sent to external constant current driver ICs that are configured for a particular current using discrete components. The power switches are either discrete, or are internal to the constant current driver ICs. In some cases, the constant current driver itself is constructed from discrete ICs and passives.

When using this method, choose the different parts of the system carefully to ensure that they are able to interact correctly with each other. Calculations for the choice of these different components must be done based on the average current, ripple percentage, switching frequency, sense voltage, and more. Every time a design criterion changes, calculations lead to choosing different components. Figure 6 shows the practical implementation of such a design. Note how the microcontroller section and the constant current drivers are separated with their own associated circuitry.

Figure 6: MR16-based LED ballast using the traditional method.

PowerPSoC method

As explained earlier, PowerPSoC implements current control with its integrated hysteretic controllers. This means that the current through the channel is being monitored continuously, during both ON and OFF periods. To achieve this, there must be access to both sides of the load, so that the switch can be on one side (the high versus the low side of the load) and the sensing element (the resistor in this case) can be on the opposite side. This topology, where the load is "floating" between the various elements of the circuit, is called a "floating load buck." LEDs are loads that lend themselves well to this kind of topology, since they are constant current versus constant voltage loads. PowerPSoC implements the floating load buck topology with a high side sensing element and a low side switch, as shown in Figure 7.

Figure 7: PowerPSoC's hysteretic controller-based current control loop.

Figure 7 shows a single current control channel from the PowerPSoC device. This is called the hysteretic controller and it performs the regulation by monitoring the current in real-time and turning on/off the switch appropriately. An SR latch, shown in this figure, performs the gate drive control for the power MOSFET. A pair of high-speed comparators controls the latch. One of the inputs to both comparators is a representative signal of the actual load current.

The load current passes through a sense resistor and a current sense amplifier (CSA) inside the PowerPSoC and amplifies the low voltage across it. This CSA has multiple bandwidth settings which are easily controlled by firmware.

The Digital-to-Analog converters (DACs) set the references for both comparators. The DAC on top is programmed with the lower limit. When the current goes below this threshold, the latch is set. The lower DAC is programmed with the upper limit. When the current rises above this limit, the latch is reset. The DACs are also easily controlled by firmware, which provides dynamic run-time control to the hysteretic controllers. The control of this type is not possible for most discrete constant current drivers.

Figure 8 shows the waveforms of the schematic in Figure 7. The red waveform is the Vsense (voltage across sense resistor amplified by CSA). When it crosses Vupper (the limit set on the lower DAC), it activates the Reset input of the latch. The latch then drives its output low, and turns OFF the switch as shown by the blue waveform. The load current starts to decrease, causing the sense voltage Vsense to decrease. When it drops below Vlower (the limit set on the upper DAC), the Set input of the latch is triggered. The latch output is increased to turn ON the switch again. This process repeats continuously to maintain the average value of the load current.

Figure 8: Waveforms of the hysteretic controller.

Figure 9 represents the architecture of the hysteretic controller module in more detail. The current sense amplifier, DACs (represented by Ref_A and Ref_B), and the latch are shown as before, but with the ON/OFF timers, also. These timers ensure a bare minimum ON and OFF time, and gate the Set and Reset signals to the latch. The output of the latch (Q) is gated by the trip signal and the dimming signal. If the Trip signal asserts, it causes the output of the final gate to be low and keeps the power FET OFF. As shown in Figure 10, the dimming signal envelops the switching regulator signal. HYST_OUT shows the nature of the signal coming out of the gate (and driving the FET).
Figure 9: Hysteretic controller section of the PowerPSoC.

Since the modulators, hysteretic controller, current sense amplifier, and power switch are all internal to the device, and configurable through software, the design methodology is different. Figure 11 shows the practical implementation of a four-channel LED ballast based on PowerPSoC. Note how the single device comprises the PSoC core and the constant current drivers.
Figure 10: Signal waveforms of hysteretic controller.

Figure 11: MR16-based LED ballast using PowerPSoC.

Figure 12 shows the entire PowerPSoC device, as represented in the interconnect view of the Cypress PSoC Designer development tool. The interconnect view is divided into two distinct sections: the PSoC core and the power peripherals. The PSoC core is divided into the digital section (top) and the analog section (bottom right). The power peripherals section is in the bottom right. A magnified view of the power peripherals section is shown in Figure 13.
Figure 12: Interconnect view of the PowerPSoC in PSoC Designer.

Figure 13: Interconnect view of the PowerPSoC showing PSoC core and power peripherals.

The interconnect view shows the various blocks inside the power core of the PowerPSoC. They are aligned from left to right in the order of progression of the system signals.

The current sense amplifier blocks are designated as CSA, the modulators as MOD, and the hysteretic controllers as HYSTCTRL. The power FETs are also shown separately, although they are part of the hysteretic controller module. In addition, separate DACs and comparators are shown, which can be used for system monitoring and protection functions such as overcurrent and overtemperature shut-off. Note that these DACs are different from the reference DACs (not shown) that are part of the hysteretic controller. The reference DAC settings are part of the hysteretic controller properties.

Similar to the classic PSoC, these blocks are configurable. There are preconfigured user modules for each of the blocks named, and each have associated parameters and APIs (similar to PSoC) that enable configuration, even dynamically, during run-time.

The procedure for placing, configuring, and connecting these blocks (referred to as user modules) are described in the Design Procedure section.

Accompanying hardware and software

Accompanying hardware and software The software tool used in this project is PSoC Designer. The tool is available for free download at

The firmware discussed in this article is made specifically for the CY3268 PowerPSoC demo board. This demo board can be purchased from Hotenda using the manufacturer part number CY3268.

Design procedure

Figure 14 provides a simple flow chart, outlining the intent and flow of the firmware design exercise that the remainder of this article explores.

1. Component and parameter configuration will be considered first. Before the chip is configured and firmware is written, a design procedure, which considers the circuit parameters and components, must be executed. Refer to the application note AN52699 – "Floating Load Buck Topology for HB-LEDs" for details, and a design example, on how to choose the various components of a floating load buck circuit such as the inductor, Schottky diode, capacitor, and sense resistor.

Figure 14: Firmware design flow.

The following parameters and components need to be considered with respect to firmware design:

  • Average current
  • Ripple percentage
  • Sense resistor value
2. Choosing the sense resistor is a tradeoff between the desired sense voltage and power loss in the resistor. In addition, the sense resistor must be chosen such that the voltage across it is under 150 mV. For example, choosing a 0.2 ohm resistor for a 1 A current would be exceeding the limit. A smaller sense resistor (e.g. 0.1 ohms) must be chosen.

3. The large gain of 20 on the CSA enables a small sense resistor. For instance, at a current of 1 A with a resistor of 0.1 ohms, the voltage across the resistor is 100 mV. A gain of 20 brings this up to 2 V. Therefore, to reduce power loss, the sense resistor can be small. It is also preferred that the DAC references are kept close to half the level of the full-scale voltage to give headroom on either side.

4. After choosing Rsense, you also need to select the hysteretic controller's DAC references. These parameters, together with the allowed ripple, are used to perform this calculation according to the formula:

From the previous point, gain (CSA) is 20. The DAC full-scale voltage is explained in the next point. The current values Ilow and Ihigh are determined by the formulas:

5. For example, a 20 percent ripple for a 1 A current would yield:

6. The DACs inside the hysteretic controller have a choice of two full-scale voltage levels: 1.3 V and 2.6 V. The 1.3 V range has a smaller resolution step of 5 mV, and the 2.6 V range has a resolution of 10 mV step.

In this case, if Iavg is 1 A and Rsense = 0.1 ohms with a ripple of 20 percent (usual practice), the current swings between 1.1 and 0.9 A. With a gain of 20 on the CSA, the sense voltages are 2.2 V and 1.8 V. Therefore, the full-scale range of 2.6 V is chosen. Now, using Equation 1:

Or Equation 2:

In hex values, these are:

Note that the result obtained from applying Equation 2 is not a round number. The result must be rounded off before configuring the DAC in firmware. In practical implementations, the resolution of the DAC and tolerance of the resistor affect the actual load current level.

Hex values are acceptable as parameters when using the APIs to modify the DAC references. When using the interconnect view to set the DAC references, they must be in decimal form.

Dimming can either be performed by one of the available digital modulators or by linear dimming, where the load current is varied to vary intensity. PowerPSoC is enabled to perform linear dimming because the DAC references can be changed dynamically through firmware.

At this point, all the external components and parameters for the modules inside the PowerPSoC are decided. The next step is to create a project in PSoC Designer, place all the user modules, configure them, and write firmware to achieve the desired functionality.

For first-time users of PSoC Designer, it is recommended to watch the training video available at Although the lab in the video is for a different device, it still provides useful information for using PSoC Designer.

Device configuration

1. Open PSoC Designer and create a new project (File < New Project…). After naming the project, click [Device Catalog], and select the appropriate PowerPSoC device by clicking the [lighting] tab and finding a device with a part number ending in D0X or G0X. Figure 15 shows that the CY8CLED04D01 device (four channels with 1 A per channel integrated FETs) is selected. A description of each of the devices can be found in the device datasheet.

2. The project is now created. In the User Modules window (see Figure 16), expand the [Power] tab. This section contains the list of user modules that are unique to PowerPSoC. Figure 16 shows where this tab is located in the interconnect view.

3. Select and place the CURSENSEHW user module by double clicking on it, or right-click and select "Place."

Figure 15: PowerPSoC device selection.

Figure 16: Power user modules.

4. The CSA is placed in the first available empty slot in the interconnect window. In this case, it ends up being called CURSENSEHW_1, and can be renamed using the properties window shown in Figure 18. Selecting it displays its properties under the properties window.

Figure 17: Placement of CSA user module.

5. The only parameter for the current sense amplifier user module is "Bandwidth." There are multiple settings to the bandwidth parameter. The selected setting depends on the switching frequency. At higher frequencies, a higher bandwidth is warranted. At lower frequencies, setting the bandwidth lower can provide better noise immunity to the amplifier. Note that the bandwidth can also be reconfigured by API calls in the firmware.

Figure 18: Current sense amplifier properties.

6. Select and place one of the modulators in the MOD block. There is a choice of PWM16HW, PrISM16HW, or DMM16HW based modulators. They are all signal density based digital modulators (up to 16-bit), but they perform the modulation in different ways. Detailed information about each of the modulators is available in the user module datasheets. Right-click on the user module in the user modules section or the workspace explorer, and select the data sheet option to open the user module datasheet.

Figure 19: Placement of modulator user module.

7. For the purposes of this example project, select and place the PRISM16HW user module. It occupies the first available MOD block, as shown in Figure 18. The PrISM modulator uses a Cypress patented stochastic signal density modulation (SSDM) technique to achieve signal density modulation while spreading the frequency spectrum of the output.

8. The modulator block has several configuration options. To start with, in the Global Resources window (see Figure 28) there is a property for the MOD clock source. This provides the reference clock to all of the modulator blocks. There is an option of 24 MHz or 48 MHz, denoted by Sysclk or Sysclk*2.

9. The output frequency of the PrISM block depends on the input frequency. The clock scaler parameter (see Figure 20) decides the final input frequency of the MOD block. Fin = MOD clock/clock scaler. The maximum output frequency is Fin/2 and minimum is Fin/(2n – 1), where n is the dimming resolution in bits. Refer to the application notes AN49262 "Modulation Techniques for LED Dimming" and AN47372 "PrISM Technology for LED Dimming" for more information on the output signal of different modulators. The MOD clock is set to Sysclk and the scaler is set to 30. Therefore, Fin is 800 kHz. This means Fout(min) = 800 kHz/255 = 3.14 kHz, and Fout(max) = 800 kHz/2 = 400 kHz. This avoids flicker, yet switches slower than the switching frequency (assumed at 1 MHz). Flicker refers to the perception of the eye. As long as the LED is turned on and off faster than 120 Hz (at the bare minimum), the persistence of vision of the human eye makes it seem that the LED is continuously lit.

Figure 20: PrISM modulator configuration.

10. The "Dimming Resolution" parameter represents the bit-width of modulation. For instance, for an 8-bit modulator, the value would be eight. "Signal Density" refers to the duty-cycle equivalent of the PWM output. The duty cycle percentage is (Signal Density + 1)/(2Dimming Resolution). In this example, a value of 127 corresponds to an overall signal density of 50 percent ((127 + 1)/28). This parameter can be changed in firmware, or set to a particular value for startup of the LEDs. Configure the modulator as shown in Figure 20. The modulator can also be reconfigured dynamically using firmware API calls.

11. Finally, the "HYSTCTRL" user module is selected from the Power section and placed like the other modules. The configuration of this module is most significant.

Figure 21: Placement of HYSTCTRL user module.

12. In the HYSTCTRL_1 properties, set the "Gate Driver" to "internal" to use the internal FETs. If external FETs are driven using the external gate drive pins, this option is set to "external." The "default" gate drive strength is sufficient to drive a MOSFET with a gate capacitance of 4 nF with a rise/fall time specified in the datasheet. Therefore, the 50 percent option drives half the impedance with the same rise/fall time.

13. The "RefHigh" and "RefLow" are the high and low trip points of the hysteretic controller or the two DAC references. These can be left untouched at this point and configured using the firmware. If required, enter the decimal DAC references calculated earlier using the equations. In this example, the DACs are configured for 175 mA with a 30 percent ripple.

Figure 22: HYSTCTRL properties.

14. The feedback input denotes the current feedback to the hysteretic controller. The parameter menu allows the option of using the corresponding CSA or a function pin. This allows the use of an external feedback mechanism. In this case, configure it to receive input from CSA0 as shown in Figure 23.

15. Set the DACVoltageRange according to what was used to configure the DAC references. The options are 1.3 V with a 5 mV step, and 2.6 V with a 10 mV step. However, all these parameters can be reconfigured dynamically using API calls in firmware.

16. The Dim input parameter provides the option of modulating the channel with any of the internal modulator blocks, or from an external modulator through one of the function pins. In this case, it is MOD0. Note that the configuration of the last two parameters are represented by actual connections in the interconnect view as shown in Figure 21.

17. The "trip input" parameter is useful when the detection of a certain condition needs to shut down the system loop. One of the auxiliary comparators, or an external input through the Function IO pins, can be used to provide a trip input to the hysteretic controller. These comparators can have one of their inputs fed from the auxiliary DACs as references for the condition to be detected. For instance, an overtemperature condition can be sensed by a thermistor and fed to one of the comparators. If the trip function is not desired, it can be set to VGND.

18. The "TimerDelay" parameter provides a choice of using the minimum on/off timer (with different options) when switching at high frequencies. In situations when the current goes from the peak to the valley (or vice versa) faster than the loop can respond, these timers are required to ensure that the hysteretic controller does not keep the switch continuously on or off.

19. Configure the other three channels in the same method. The average currents can be varied for the other channels if desired. The final interconnect view in Figure 23 shows how one channel must look at the end of placement and configuration of all modules.

Figure 23: Final interconnect view of power core for one channel.

20. There are standalone hardware comparators in the power core. These comparators are not required for the current or dimming control, but can be used for additional functionality such as overcurrent or overtemperature protection. The comparator can monitor inputs from the CSA or from one of the function pins to monitor external signals. The other input (reference) can be obtained from function pins, or from the standalone DACs.

Figure 24: Placement of CMPHW user module.

21. The properties window of the CMPHW user module (see Figure 25) shows a possible configuration of the user module. The fast mode is useful when a very fast hardware response is needed, such as for overcurrent monitoring. The slow mode can be used when a slower changing parameter, such as temperature is being monitored. This uses less power. In addition, the 10 mV hysteresis can be enabled.

Figure 25: Placement of CMPHW user module.

22. To work with these comparators, the standalone DualDAC8HW user modules can also be used. These DACs are used to provide a reference to the comparators for protection functions.

Figure 26: Placement of dual DACs.

23. Through the interconnect view, the significant parameter that can be configured is the voltage range. For the 2.6 V range, the steps are in 10 mV increments. For the 1.3 V range, the steps are in 5 mV increments. The 8-bit data for each of the DACs is written through firmware API calls (for example, when data = 0x80, the voltage is 1.3 V for the "2.6 V Mode" and is 0.65 V for the "1.3 V mode."

Figure 27: DualDAC8HW user module configuration.

Figure 28 shows the settings of the global resources in the interconnect view. The last five parameters are significant to the PowerPSoC in particular. The "AINX connection" connects any of the four CSAs to the analog bus, in order to monitor its output using an ADC and monitor load current. "AINX mode" configures the amount of bias current that is used to bias the modules in the power core. "MOD clock" is the input clock to the modulators in the power core with options of 24 MHz and 48 MHz. "Bias Generator" enables or disables the current bias generator. This must be set to "enable" for the power peripherals to function. The final parameter "Switching Regulator" enables or disables the 5-V regulator. Refer to the PSoC Technical Reference Manual on the correct usage of the regulator and its relationship with software. However, the general rule of thumb is to enable it if the regulator is needed.

Figure 28: Global resources parameters.

24. After the configuration of all modules is complete, use the "Generate Configuration Files" button or menu option (from the Build menu) to generate the application files. Any errors will show up in the [Output] tab.

From the workspace explorer, open the source file "main.c" as shown in Figure 29. This opens the main source file with two header files included and an empty main function defined. The code provided in the Appendix goes in main.c. It goes through the process of starting up all the modules.

Figure 29: Accessing firmware source code from Workspace Explorer.

25. You must note the startup sequence of the user modules in these function calls. In a high power system that PowerPSoC plays a role in, it is important that the feedback and control system are on before the current drivers are turned on. This is called sequencing. In this case, the current sense amplifiers must be started before the hysteretic controller user modules. If only one channel is being started up, there could be a situation when the hysteretic controller starts up before the current sense amplifier has finished starting up. In this case, a small delay must be inserted in firmware to avoid this.

26. After the code is entered, use the build icon or choose the option "Build Project" from the Build menu. This compiles and links Figure 27: DualDAC8HW user module configuration. Figure 28: Global resources parameters. Figure 29: Accessing firmware source code from Workspace Explorer. 37 all the files required by the project. Ensure that a valid C compiler (ImageCraft) is installed; otherwise, a build error occurs. PSoC Designer comes with a free ImageCraft version. If the project builds without any errors or warnings, then it is ready to be programmed onto the device.

Project Firmware

At, you'll find a PSoC Designer project zip file containing code that has implemented the configuration and the firmware described in the previous section. The project drives all four RGBA LEDs on the PowerPSoC evaluation board with a current of 175 mA and 30 percent ripple. The dimming modulation is set to a duty cycle of 50 percent.

The project can be directly opened in PSoC Designer, built, and programmed to quickly demonstrate the capabilities of the device and firmware. The project, when built with the ImageCraft compiler, occupies 2.5 KB (out of a total 16 K) of flash memory and 26 bytes (out of 1 K) of RAM. To program the device with the attached firmware, a PSoC MiniProg programmer (part of the CY3210 kit) should be used. Follow these steps to program the device:

1. Connect the MiniProg to the PC with the USB cable.

2. Connect the MiniProg to the ISSP header (5-pin header) on the board.

3. In PSoC Designer, in the menu, click Program > Program Part…

4. In the Program Part window, the "Port Selection" field should show that a MiniProg1 is connected.

5. If the board is not powered yet, set "Acquire Mode" to Power Cycle. If the board is powered, set to Reset.

6. Verification can be either setting.

7. Power Settings should be 5.0 V.

8. Click the Program Button (bottom right corner of the window). Wait until the progress bar completes. The status should say "Operation Succeeded."

9. If the board is not yet powered, then supply power to the board. All four LEDs should be glowing.

Figure 30: Programming the device (already powered).

The CY3268 PowerPSoC demo board can be used as the ideal platform to quickly evaluate the device. It has an ISSP header for programming, the PowerPSoC on-chip debugger (OCD) device CY8CLED04DOCD and a debug port to enable debugging, and four channels of LEDs. Additionally, it has five CapSense buttons connected to PowerPSoC GPIO pins.

If a custom board is being made, ensure that an ISSP header and an OCD device are used to enable easy debugging and programming.

Figure 31:CY3268 PowerPSoC evaluation board.


PowerPSoC presents a powerful new standard of designing high power systems together with intelligence using software tools. The combination of the well-established PSoC core, along with high performance power electronics, enables integrated, low cost, small designs that differentiate products from others using conventional methodologies.

The firmware example project shows how simple it is to get a power management circuit up and running with minimal investment in putting the system together. In addition, easy configuration of the circuit using firmware allows quick and inexpensive design cycles. This results in quick time-to-market for end products. The flexibility of the device to be a part of different power management topologies means that a single platform can be used for a wide variety of applications. The powerful PSoC core adds a degree of intelligence that enables a safe and reliable system without increasing the complexity or cost.


// C main line
#include // part specific
constants and macros
#include " // PSoC API
definitions for all User Modules
void main(void)
  M8C_EnableGInt; //Enable global
  CURSENSEHW_1_Start(); //Start each of
the current sense amplifiers
  PRISM16HW_1_Start(); //Start each of
the PRISM modulators
  HYSTCTRL_1_Start(); //Finally start
the hysteretic controllers
  HYSTCTRL_2_Start(); //Note that
these modules are to be started only after
  HYSTCTRL_3_Start(); //CSA is turned
} //end main