Greater energy efficiency has become a key requirement in computer servers and high-performance networking equipment. The cost of cooling these systems is now a major factor in their lifetime cost as well as their own energy usage. Such systems rely on advanced microprocessors and, in the case of high-performance computing applications, general-purpose graphics processing units (GPGPUs) that are capable of billions of floating-point operations per second. These processors are often densely packed to maximize their space efficiency and each of them may have a power demand of more than 100 W when running at peak speed. As a result, thermal efficiency in power conversion is essential under demanding conditions.
To minimize losses in power distribution across the backplane of a server or switch, these systems are typically architected to use a comparatively high intermediate voltage of at least 12 V. Point-of-load (POL) converters are then used to deliver the low voltages – generally around 1 V – that these devices require. This often results in a requirement for high peak current values to handle the brief periods during which the processor will operate close to its thermal envelope.
Conventionally, POL converters have been architected for maximum efficiency at high load as this is where excess heat can be most damaging. Most POL converters in use today guarantee more than 90 percent efficiency at full load. In a densely packed server, this efficiency is vital as it ensures that standard air-cooling can remove heat quickly enough to prevent the system from overheating and the risk of processors undergoing thermal shutdown. In the modern internet-based environment, losing transactions and requests due to a sudden processor shutdown can quickly damage revenues and reputations.
However, because the system is rarely likely to have more than a fraction of the processors operating at full capacity, significant energy can be lost in the need for forced air cooling. Since the efficiency of a conventional POL converter goes down as the load reduces, a greater proportion of the cooling needs to be for the power-delivery infrastructure rather than the processors themselves. If POL converters can be made more efficient, it is possible to scale back the requirement for forced-air cooling and so as to not only reap savings in the server itself, but the surrounding air conditioning also.
Advances have been made in power conversion technology, largely focused on the problem of the amount of board area consumed by each POL converter. One trend has been an increase in switching frequency to reduce peak current demand, which helps to keep the size of passive components such as capacitors to a minimum. However, there is a limit to how high the switching frequency can be pushed, especially in high-current systems where the frequency has a greater impact. In general, during transitions, the control switch has a switching loss that is proportional to the output current multiplied by the energy supplied and the switching period itself.
A solution being pursued by a growing number of POL IC designers is to have a single input processed by more than one converter. The converters are run in sync with each other but using different phases. The oscillators in a multiphase converter are synchronized such that each phase is driven at the same frequency (f) but the phases are shifted by 360°/N, where N is the number of phases in the overall converter. The output of each individual buck phase is paralleled with the others such that the ripple frequency is Nf rather than f.
Figure 1: Channel input currents and input capacitor current for a three-phase situation.
The use of multiple phases means that the core conversion topology maintains the advantages of high-frequency operation without reducing the switching period and has the benefit of reducing over-ripple current, as the gap between pulses of current is much shorter than with a single-conversion topology. This also improves the electromagnetic interference (EMI) signature, as the rate of change of current within the converter is lower than with a conventional approach.
For a multiphase or polyphase converter, the effective operating frequency is effectively the fundamental switching frequency multiplied by the number of phases. As a result, transient response improves, which is important for advanced processors as power demands can change over the course of very few clock cycles.
The multiphase buck converter topology has more packaging advantages. Each channel converts power at a fraction of a comparable single-phase buck converter, which reduces the size of the inductors and power MOSFETs used in the design. Smaller power MOSFETs reduce dynamic losses as they have smaller parasitic capacitances. Similarly, capacitors experience lower losses because of the reduced ripple current.
Figure 2: Ripple current against duty cycle for a range of different multiphase options.
At peak demand all of the phases in the converter are active. However, as the processor slows and its power needs drop, the converter can switch off one or more of the phases, removing the switching losses of that phase from the overall energy demand. The result is a POL converter that reacts to the demands of the load on a dynamic basis. Control over phases can be assigned to a local microprocessor or to a board-level power controller using PMBus signals. PMBus commands are available that let a central power manager switch phases on or off.
Multiphase converters help minimize the external component count and simplify the complete power supply design by integrating PWM (pulse width modulation) current-mode controllers, remote sensing, selectable phasing control, inherent current sharing capability, high-current MOSFET drivers plus overvoltage and overcurrent protection features. At higher power levels, scalable multiphase controllers reduce the size and cost of capacitors and inductors.
To provide control over multiphase conversion in custom designs, Intersil’s ISL6364A
has dual PWM outputs designed for low-voltage processors and GPUs. It has a four-phase PWM to control the microprocessor core or the memory voltage regulator. Its second PWM controller is a single-phase design, which controls the peripheral voltage regulator for I/O. The part uses Intersil’s proprietary Enhanced ActivePulse Positioning (EAPP) modulation scheme to achieve a fast transient response with fewer output capacitors than standard designs.
is designed to be compliant to the specifications provided by Intel for VR12/IMVP7-class regulators. These regulators support close cooperation between the POL converter and the processor. In the case of the ISL6364A
, the controller monitors load current and reports this information using the IOUT
register to the microprocessor. The processor, in turn, if it sees current drop below a certain point, can send a low-power-mode signal to the controller via the SVID bus. The controller can then enter a lower-power mode, using either one- or two-phase operation. In an ultra-low-power mode, it can operate in single phase with a diode emulation option. After the PSI low-power signal is de-asserted, the dropped phases are added back to support heavier loads. The ISL6364A
also has support for auto-phase shedding to optimize efficiency without processor involvement.
At very low load levels, even a single phase can lose efficiency. DC/DC controller vendors have implemented techniques such as pulse-skipping or burst mode. In burst mode, the switching circuit only activates when the output voltage begins to move out of regulation.
In a device such as the LTC3856
from Linear Technology, a sleep signal is activated when the average inductor current is higher than that of the load. During sleep mode, the load current is supplied by the output capacitor. When the output voltage drops far enough, the sleep signal is deactivated and the converter activates on the next cycle to supply power until the sleep signal is reasserted. Pulse-skipping mode provides lower ripple by not switching for several cycles at a time when light-load conditions are detected, albeit with reduced overall efficiency compared with burst mode. This architecture provides designers with a choice of power-saving approaches to best suit the tradeoff between efficiency and other factors, such as output ripple.
At higher load levels, the LT3856 performs automatic phase shedding and reactivation. Stage shedding operation is triggered when the onboard feedback error amplifier output voltage reaches a user-programmable voltage. At this programmed voltage, the controller shuts down one or more of its phases and stops the power MOSFETs from switching on and off. This ability to program when stage shedding takes place provides the flexibility to determine when to enter this mode of operation.
For designs that need a high degree of control over the number of phases that operate in a system, Texas Instruments has the TPS40140, a versatile controller that can operate as a single controller or 'stacked' in a multi-controller configuration. The TPS40140 has two channels that may be configured as multiphase for a single output or as a dual output with two independent output voltages. However, the two channels of a single controller always switch 180 degrees out-of-phase.
In a multiple device system it is generally desirable to synchronize the clocks of each device to minimize input ripple current as well as radiated and conducted emissions. This is accomplished by designating one of the controllers as the master and the others as slaves. To create a 12-phase system, the designer needs to add five slave devices, interconnected using the PHSEL and CLKIO lines and then set up the way in which they respond to the master’s clock signal.
The slaves detect the correct clock signal from the master CLKIO signal through the use of series 39 kΩ resistors on the PHSEL output from the master. Depending on how the master is set up, the CLKIO signal generates either six or eight clocks for each cycle of the switching period. To further increase the total current capability to twelve phases, or to increase the number of outputs, five slave controllers are used with two resistors set on the PHSEL line. To achieve 12-phase operation, the ILIM2 pins on three of the slave controllers are tied high so that they trigger on the falling edge of their corresponding CLKIO signals rather than the default rising edge.
Figure 3: Twelve-phase configuration using six TPS40140 devices.
As energy efficiency continues to be an area of focus for server designers, the multiphase POL strategy is likely to become more common and we will see further improvements to the way in which the circuits react to fast changes in load requirements and to low-load conditions.