MCUs are key elements in just about every connected device and are expected to drive the deployment of millions of “end nodes” for the IoT (Internet of Things). End nodes include a wide variety of elements such as meters, sensors, displays, and pre-processors, as well as data-fusion components that combine multiple functions in a single device. A common requirement in IoT end nodes is the need for small size since these devices are typically constrained to a very small footprint. Consider, for example, wearable devices; small size and small weight are critical for customer acceptance.
MCUs in small packages provide the perfect element for controlling size-constrained IoT end-node applications. Many MCUs also have additional features that make it easy to fit a very powerful design into a pin-constrained form-factor. Flexible pin assignment, autonomous operation, and intelligent peripheral interconnect are some examples of advanced features small-pin-count MCUs have that further enhance their ability to make a big impact on size-limited applications.
Small-size packages are a key enabler for fitting MCUs into the confined board space allowed by the majority of IoT end points. Wearable devices, in particular, will have very limited space, but will still need significant processing power and storage to implement the front-end functions required by sensors, sensing aggregators, and controllers. Chip Scale Packages (CSPs) provide an ultra-small footprint without requiring exotic manufacturing capabilities. The Freescale Kinetis KL03 20-pin CSP MCU Family, for example, uses a 20-pin CSP format with a 1.6 x 2.0 mm 2-package size. As shown in the illustration in Figure 1, the 20-pin device has 20 solder bumps at a fine pitch to fit into a minimum amount of board space.
Figure 1: Freescale’s KL03 family MCU in a chip-scale package. (Courtesy of Freescale)
Small packages need not provide small processing power, however. The KL03 has a powerful 48 MHZ 32-bit ARM Cortex-M0 processor core with 32 KB of on-chip Flash and 2 KB of on-chip SRAM. Multiple serial ports (LPUART, SPI, I²C) make it easy to connect the MCU to standard peripherals. A 12-bit ADC with an analog comparator and internal-voltage reference support common sensing requirements. Timing operations, very common in IoT applications, are supported with a low-power timer, and a real-time clock. A Pulse-Width-Modulation (PWM) timer is also available to simplify mechanical-control applications. This much power in a very small 20-pin CSP format is an excellent example of the big capabilities that are available to designers.
MCU manufacturers do not stop with only offering powerful CPUs in small packages, however. Adding intelligent integration – specialized hardware that can minimize external supporting devices – is another way to pack as much functionality into a small amount of board space. As an example, how often have you needed a few extra simple components to combine external functions so they can fit into a pin-limited device? Have you also needed to do this as a way to speed up processing of input signals when CPU-managed bit-sensing loops were too slow or used up too much valuable CPU time? MCU manufacturers are beginning to address these needs for more logic integration by adding user logic on-chip.
One example of this type of intelligent integration is the Microchip PIC16(L)F1503 MCU. This device includes a small amount of configurable logic on it, using what are called Configurable Logic Cells or CLCs. These logic cells can be used to create simple logic functions from device inputs and internal signals. The CLC outputs are available for use at device outputs or with internal peripherals. A diagram of a CLC is shown in Figure 2.
Figure 2: PIC on-chip configurable logic block diagram. (Courtesy of Microchip)
Up to 16 inputs can be selected and then a logic function is available to create four generated outputs. Each output can be individually enabled, polarity selected, edge detected, or registered – depending on what the output is being used for. The eight possible logic functions include a selection of AND-OR, OR-XOR, latches, and registers – all the common functions needed on a pin-constrained device. For example, you can integrate some simple gates from your board into the MCU or you can create some simple functions to eliminate CPU cycles normally used to combine or condition device inputs.
Note that peripherals can now be combined using hardware instead of CPU-intensive polling and “bit banging” techniques. This turns simple peripherals into much more intelligent ones, so they can operate independently of CPU oversight. An ADC, timer, and interrupt controller can now be easily combined into a complete sensing sub-system, with CPU intervention only required when the sub-system requires it, perhaps when an out-of-bounds or time-out condition occurs.
For an overview of Microchip’s Configurable Logic efforts see the Product Training Module aptly named “Configurable Logic Cell.”
Efficient pin allocation
One of the issues with using a small-pin-count MCU is getting the right function assigned to an IO pin. In many MCUs an output pin is shared by multiple peripherals and it is possible that the peripherals you want to use have conflicting IO assignments. This can make it difficult to get the amount of functionality you want in the smallest package. You may need to use a larger package for your particular resource mix. IO assignment can also impact board layout and signal routing. You may end up using more board space or more signal layers than the ideal case if pins are not placed in convenient locations.
Some MCU manufacturers are addressing these limitations with increased pin-assignment flexibility. NXP, for example, has added an IO-pin matrix that can be used to “swap” pin locations for a wide range of on-chip peripheral signals. As offered in the NXP LPC82x family (Figure 3), the IO-switch matrix provides a swapping capability on 29 IO pins. GPIO signals, timers, serial peripherals, and even analog inputs can be arbitrarily switched to the device pin you desire.
Figure 3: IO-pin switch matrix on the NXP LPC82x family. (Courtesy of NXP)
The switch matrix provides full connectivity from any of the 29 IO pins to any of the internal peripherals. (With only a few exceptions, for example, the JTAG pins are always assigned to PIO_0 to PIO_4 when the part is in boundary-scan mode and PIO_4 is used for the wake-up from deep power down. These exceptions are understandable since the associated functions are so device specific.) The switch matrix is so flexible you can even assign multiple peripheral inputs to the same device pin to reduce total pin count even more. The inclusion of a switch matrix on the LPC82x MCU dramatically improves your ability to get just the right signal on just the right pin allowing you to use the minimum-sized package and board space for your specific application.
NXP also offers engineers a Product Training Module entitled “Introduction to IO Switch Matrix,” which can be found on the Hotenda website.
Efficient use of MCU pins can be supported by MCU hardware features that connect input pins and internal peripherals. This allows the creation of pin-efficient autonomous peripherals that require little or no CPU intervention. Consider the Renesas RL78/G13 MCU family (for example, the R5F1007DANA#U0
), which has an Event Link Controller (ELC) that selects various events (such as external input interrupts, internal interrupts, timer interrupts, or compare match results) and connects them via hardware to the desired peripheral input. As shown in Figure 4, it uses an external interrupt to trigger an Analog-to-Digital conversion. This can be accomplished without involving the CPU, perhaps even while the CPU is in a low-power sleep mode. This efficiently uses IO resources while keeping power dissipation as low as possible, another key requirement for most IoT applications.
Figure 4: Use of the Event Link Controller on the Renesas RL78/G13 MCU family. (Courtesy of Renesas)
Low-pin-count packages are ideal for many IoT applications, and when using these small packages you need not give up powerful processing capabilities. Efficient pin mapping via an IO Switch Matrix, Event Link Controller, or on-chip Configurable Logic Cells can improve pin efficiency to make sure you are using a minimum of board space in the most size-constrained IoT applications.
For more information on the parts discussed in this article, use the links provided to access product pages on the Hotenda website.