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The power delivery systems in telecom applications now have to cope with large arrays of high-current CPUs, potentially consuming hundreds of watts of power. To increase efficiency, telecom PSUs employ switching topologies to convert electricity from the grid supply to a 48 V DC output that is then distributed to line cards in the rest of the system. The problem is that switched-mode power supplies present nonlinear impedance to the grid because of the structure of their input circuitry.
The input circuit usually comprises a half-wave or full-wave rectifier followed by a storage capacitor that maintains the voltage at a value close to the peak voltage of the input sine wave. It is recharged by the subsequent half wave. This topology only draws current from the input when the grid supply peaks; this pulse contains enough energy to sustain the load until the next peak. The current pulse may last for no longer than a quarter of the cycle, and the current supplied during the pulse must be at least four times the average current.
The resulting current waveform is, compared to the sinusoidal input, heavily distorted with a large number of strong harmonics. Only the fundamental component produces actual power – the remaining peaks are responsible for apparent power. This difference is represented by the power factor, which for all cases, except a pure sine wave, will be less than unity.
The harmonic distortion has an adverse effect on other loads on the same supply. The distorted current causes additional heating in the wires and electrical distribution gear. As a result, legislation has come in worldwide to limit the harmonic distortion of switched-mode PSUs, in addition to controls imposed by the utilities themselves on high-power equipment. Electrical equipment with an input power requirement of 75 W or more, supplied in Europe and Japan, must comply with the IEC61000-3-2 standard. The standard specifies the maximum amplitude of line-frequency harmonics up to and including the 39th harmonic. As core telecom switches are responsible for high loads, they need to limit harmonic distortion and maintain a high power factor.
Power factor correction (PFC) shapes the input current of the PSU to maximize the real power level from the grid and minimize harmonic distortion. Ideally, the electrical appliance should present a load that resembles a resistor rather than the reactive load of a bare switched-mode PSU. Instead of a series of narrow peaks, the current waveform will follow the same sine wave profile as the AC input and will be in phase with it. This corrected waveform minimizes losses as well as interference with other devices being powered from the same source.
The PSU for a telecom system is generally designed to have a two-stage structure. The front-end stage is used for PFC, while the second stage is a DC/DC conversion circuit that provides the desired regulated DC output. In principle, a simple inductor could provide adequate PFC for many switch-mode PSUs. The inductor acts to spread the current out in time and, in turn, reduces the harmonics far enough to meet most regulations. The drawback is that the inductor needs to be relatively large – its size and cost is generally unacceptable in the context of a densely populated telecom server or switch.
Figure 1: The two-stage architecture of a typical telecom PSU showing the PFC pre-regulator and DC/DC regulator stages.
In practice, the PFC stage in a telecom system is a switched-mode PSU in its own right. The most commonly used topology is that of a boost converter, which adds a switching power-control circuit to the series inductor of a pure passive PFC implementation. The boost converter maintains a continuous input current – this can be forced to track the changes in line voltage to maintain a high power factor. However, within the broad category of boost converters, there are a number of circuit architectures available that provide telecom PSU designers with a high degree of control over efficiency, a key consideration as standards such as Energy Star continue to push losses from PSUs down.
A number of PFC controllers that support continuous conduction – a technique that minimizes current stress – and use average current mode control to achieve a smooth output waveform. International Rectifier’s IR1152 is an average current-mode controller that employs the company’s one-cycle control algorithm.
The one-cycle control algorithm uses two control loops: a slow outer voltage loop and a fast inner current loop. The outer voltage loop monitors a voltage sense pin and generates an error signal that controls the amount of current that is fed into the PFC converter. The inner current loop maintains the desired sinusoidal profile with cycle-by-cycle control over peak current.
The Infineon ICE2PCS02G can switch from continuous conduction mode to discrete conduction mode under light load conditions, which generates higher harmonics but stays within legislative limits and maintains high efficiency. Both the IR1152 and ICE2PCS02G have a number of protection circuits to guard against situations such as brownouts and overvoltage conditions.
An alternative strategy is to use critical, transition, or boundary conduction mode – a scheme that is popular in lower power systems. However, the use of interleaving makes it possible to employ stages in parallel to increase the overall output power and still obtain the advantage of using smaller passive components. Such paralleled converters can operate out of phase to each other to minimize ripple current when summed at the output. This, in turn, reduces the output filtering requirements.
Figure 2: The current generated by the regulator is provided by a series of ramps in boundary conduction mode that follow the profile of the input voltage, scaled to the required power level by a factor of k. In this mode, each ramp starts as soon as the last completes.
Figure 3: The CS1501 switches between discontinuous mode and quasi-boundary conduction mode as power requirements change. The current ramps separate in the discontinuous mode.
Figure 4: The architecture of a typical semi-bridgeless PFC circuit.