Phase-locked loops (PLLs) have advanced considerably since the first one was developed by Henri de Bellescize in the 1930s. Over the nearly 80 years, phase-locked loops have evolved and now come in three types: the PLL, digital phase-locked loop (DPLL), and all digital phase-locked loop (ADPLL). The PLL consists of all-analog components and was the standard loop until the DPLL, which contains both analog and digital components, was developed in the 1970s. DPLLs have a digital phase detector and an analog oscillator and loop filter on the back end. A few years later, the fully-digital ADPLL was developed. Advances continue and new PLL architectures were shown recently at ISSCC (International Solid-State Circuits Conference).
The PLL is the most suitable circuit architecture to perform the diverse tasks necessary in several types of applications. For example, in transceiver applications, PLLs are used to generate high-frequency LO signals with low-phase noise for both up-conversion and down-conversion of the transmitted and received signals. In high-speed data communications, PLLs are used to obtain low jitter performance. Also, when used as clock generators for large processors, wide-frequency range, fast-locking time and low-power consumption are necessary.
Digital fractional-N PLLs – a type of Multibit PLL – intended for today’s wireless systems use high-resolution and high-linearity time-to-digital converters (TDCs) in order to meet the stringent integral phase noise requirements. A high-performance TDC can complicate the synthesizer design and consumes a large amount of the power budget, which further leads to a poor jitter-power compromise.
One ISSCC paper described a 2.9- to 4.0-GHz fractional-N digital PLL based on a TDC that achieved a jitter of 560 fs rms (from 3 kHz to 30 MHz) at 4.5-mW power consumption. The circuit synthesizes frequencies between 2.92 and 4.05 GHz with 70-Hz resolution. (Paper 5.1, ISSCC 2011)
Figure 1: Digital fractional-N bang-bang PLL block diagram.
The PLL block diagram in Figure 1 shows the standard-cell-based digital blocks filled in gray. The TDC is a single D-flip-flop, but is referred in the paper as a bang-bang phase detector (PD). Bang-bang PDs are never used in ΔΣ fractional-N PLLs for wireless systems because they act as hard limiters on the timing error between reference and divider output, and their nonlinearity causes large, undesirable spurs and noise at the output.
Figure 2: Measured jitter over the fractional synthesized channels.
Figure 2 shows measurements with no off-clip regulation of loop parameters, over the fractional synthesized channels from 2,962 to 4,042 MHz in steps of 40 MHz and from 3,520 MHz (integer channel) to 3,540 MHz with logarithmic frequency spacing. For fractional channels causing only out-of-band spurs, rms jitter reduces to 420 fs rms. Reference spur is below -72 dBc in all cases. The core power consumption (excluding pad driver and crystal oscillator) is 4.5 mW, and the majority of the power is used in the controllable delay (49%) and the DCO (38%). This leads to a figure of merit, defined as the product of the jitter variance by the dissipated power in milliwatts, of -238.3 dB, in the worst case.
Figure 3: On the right is a block diagram of the proposed ADPLL and on the left, a typical rotary-traveling-wave oscillator (RTWO) circuit topology.
Another paper presented (Paper 5.7) built an ADPLL around a RTWO using a 32-phase embedded phase-to-digital converter (Figure 3).
The RTWO provides a natural structure for high-precision phase-to-digital conversion that does not require period normalization. The prototype in 65nm CMOS achieves a 5.6° phase resolution, which corresponds to a 3.9-ps time resolution at 4 GHz. This results in -108-dBc/Hz in-band phase noise for a 1-MHz loop bandwidth. The total power consumption is relatively large, but the fractional phase detector draws only 350 μA (0.42 mW). The performance summary is shown in Table 1.
Table 1: RTWO phase-to-digital conversion performance summary.
||1.5 (DCO core), 1.2 V (others)
|DCO core current
|Other analog current exclude output buffer
|Digital core current
||2.6 to 4.5 GHz
|In-band phase noise
||-108 to 11 dBc/Hz
|DCO phase noise
at 4-GHz output, 20-MHz offset
||5.6° (3.9 ps 4 GHz)
Using all-digital fractional PLLs instead of the integer analog PLLs, provides flexibility, portability and lower sensitivity to the analog parameters. Adaptive supply noise cancellation is effective with digital circuits, which is crucial in order to achieve the high PLL performance in a noisy environment.
For example, the CD74HC297E from Texas Instruments is a high-speed CMOS logic digital PLL. This part is pin-compatible with low power Schottky TTL (LSTTL). These devices are designed to provide a simple, cost-effective solution to high-accuracy, digital, phase-locked-loop applications. They contain all the necessary circuits, with the exception of the divide-by-N counter, to build first-order PLLs.
Figure 4: Functional diagram of CD74HC297E.
Both exclusive-OR and edge-controlled phase detectors are provided for maximum flexibility. The input signals for the exclusive-OR phase detector must have a 50-percent duty factor to obtain the maximum lock-range.
Proper partitioning of the loop function, with many of the building blocks external to the package, makes it easy for the designer to incorporate ripple cancellation or cascade to higher-order PLLs.
The two architectures above blur the distinction between analog and digital circuit design, but produce ongoing advances in analog state-of-the-art technology. In addition, these new techniques promise better performance over currently-available PLL architectures.
Engineers involved in PPLs gained valuable insight at ISSCC, especially related to frequency synthesizers and clock generators, which are essential building blocks in almost all modern electronic systems.
Two other notable PLL-related papers at the event were:
- “A 570-fs rms integrated-jitter ring-VCO-based 1.21-GHz PLL with hybrid loop,” to address the problem of sampling clock jitter significantly degrading the circuit performance and dynamic range of an ADC (Toshiba)
- “A scalable sub-1.2-mW 300-MHz-to-1.5-GHz host-clock PLL for system-on-chip in 32-nm CMOS,” creating a low power circuit PLL for the host clock SoC in mobile applications (Intel)
- “2011 Digest of Technical Paper, IEEE ISSCC, Volume 54, ISSN 0193-6530, Paper 5.1 (Politecnico of Milan): A 2.9-to4.0GHz fractional-N digital PLL with bang-bang phase detector and 560 fs rms integrated jitter at 4.5 mw power. Paper 5.7 (Panasonic, Cupertino, CA): A rotary-traveling-wave-oscillator-based all-digital PLL with a 32-phase embedded phase-to-digital converter in 65nm CMOS.’
- “Digital Phase Locked Loops, Mike DeLong, 13 May 2004”