Typically, motherboards deployed in today’s embedded telecom, server, and storage applications contain over a dozen different point-of-load (POL) regulators that deliver anywhere from less than 1 A up to about 30 A of output current. These buck-type of synchronous POL regulators normally steps down an intermediate bus voltage to the supply voltages required by the load ICs.
Driven by market requirements for small size, low cost, fast transient performance, and power sequencing, these buck-type POL regulators are operated at high frequencies using synchronous rectification and voltage-mode control techniques. Although such schemes deliver high efficiency with high power density, they also result in high jitter and noise that are unacceptable in competitive, new generation systems.
The good news for designers is that power semiconductor suppliers like International Rectifier have addressed such problems by developing a new pulse-width modulator (PWM) scheme for achieving jitter-free operation at high frequency and a narrow duty cycle using a novel voltage-mode controller. It has been implemented in the maker’s synchronous buck regulator IR3899, which also contains built-in features that provide improved flexibility in implementing POL designs.
A typical voltage-mode control scheme used in a synchronous buck regulator is depicted in Figure 1. As shown, the error amplifier in this scheme typically receives a sample of the output voltage and compares it with a precision reference voltage to produce an error voltage (VERROR
) at the output of the error amplifier. This output is then fed to a high-speed PWM comparator which also receives a ramp signal (VRAMP
). Next, the output of the PWM comparator is fed to the reset input of a latch like the S-R flip-flop whose other input set is driven from a periodic clock signal generated internally. This periodic clock is generated at a fixed frequency and is usually user programmable with an external resistor or capacitor.
Figure 1: Traditional voltage-mode pulse-width-modulated (PWM) controller.
Consequently, when the output voltage changes due to variations in input voltage, load, temperature, or any other such variable, the amplitude of the VERROR
signal changes. As a result, it varies the PWM comparator threshold and the pulse-width of the PWM comparator output. By adjusting the pulse-width (duty cycle), the output voltage can be kept constant for any variation in input voltage, temperature, load, and more. The control FET and synchronous FET (Sync.Fet) are driven by HDrv and LDrv pulses from their driver section.
As described in the design feature titled “Voltage-Mode Control Scheme Improves Buck Converter Performance At High Frequencies
” by Suresh Kariyadan and Parviz Parto of International Rectifier,¹ the ramp starts at the rising edge of the PWM signal in a traditional voltage-mode controller, and intersects the VERROR
signal at a low-voltage level, which normally is the nonlinear region of the ramp for narrow duty-cycle operation. Kariyadan and Parto explain that this nonlinear region produces more jitter. The authors then compare the traditional voltage control with the new proposed control scheme developed by IR engineers. As illustrated in Figure 2, the ramp starts earlier than the falling edge of the set signal, and thereby intersects with the VERROR
signal in a more linear region. In this way, it produces a minimum amount of jitter. According to IR, the new voltage-mode scheme can even produce zero duty cycle if the reset signal rises before the set signal falls.
Figure 2: Comparing theoretical waveforms for the proposed voltage-mode control scheme with the traditional voltage-mode controller.
As mentioned earlier, the patented new scheme has been implemented in the manufacturer’s voltage-mode regulator IC IR3899. To compare the jitter performance of the traditional voltage-mode control with the new method, IR engineers generated experimental switch-node waveforms for the two schemes for a switching frequency of 600 kHz with a narrow pulse-width. The measured switching waveforms show that for a 12 V input DC/DC converter with 1.0 V output at 9 A load using traditional voltage-mode control at 600 kHz switching frequency, the jitter performance is 17.6 ns (Figure 3). Using similar input to output ratio and load at 600 kHz frequency, the jitter performance improves to 3.3 ns with the new scheme as shown in Figure 4.
Figure 3: The measured switching waveform, for a 12 V input DC/DC converter with 1.0 V output at 9 A load using traditional voltage-mode control at 600 kHz switching frequency, shows that the jitter is 17.6 ns.
Figure 4: Using the new voltage-mode control scheme for a 12 V input DC/DC converter with 1.0 V output at 9 A load and 600 kHz switching frequency, the jitter is reduced 3.3 ns.
The engineers observed that with high step-down ratio and higher switching frequency, jitter performance gets even better with the new proposal while it worsens with the traditional approach. For instance, the IR engineers generated similar switch-node waveforms for a DC/DC converter with 16 V input and 1.0 V output for a 9 A load at 600 kHz switching frequency. It was observed that jitter performance with the traditional method deteriorated to 32 ns, while with the new scheme it improved to 1.3 ns.
The new voltage-mode PWM control scheme has lot more to offer than simply improving jitter performance. According to the IR tech article,¹ the new modulator scheme guarantees a monotonic startup of the output voltage, as well as improves transient response. Also, since the new scheme is capable of generating very-narrow pulse-width close to zero, a clean start-up is ensured. Since the reset signal can rise before the set signal falls, zero duty-cycle can be generated without any DC offset in the ramp signal. Practically speaking, measured DC offset is only 150 mV in the new scheme and can operate with higher closed-loop bandwidth. So during startup, the VERROR
signal can take over the control of the duty cycle much earlier, per IR’s design feature.
Regarding the improved transient response, IR engineers indicate that the transient response improvement is achieved by operating at a higher switching frequency and higher closed-loop bandwidth. The effects of switching frequency and bandwidth on transient performance and capacitor requirements are discussed in this article based on measurements on a prototype buck converter that operates at VIN
= 12 V and VOUT
= 1 V at a 1 MHz switching frequency. The inductor used is a 0.33 μH surface-mount device (Vishay IHLP2525CZER) and the output capacitor used is a TDK 22 μF, X5R, 6.3 V, 0805 ceramic type (C2012X5R0J226M).
Another feature offered by the new voltage-mode control method is the feed-forward function that ensures stable operation while maintaining the load-transient performance over a wide variation of the input voltage. Figure 5 shows that the PWM ramp amplitude signal (VRAMP
) changes proportionally with respect to input voltage to maintain a constant ratio of VIN
. It keeps the modulator gain constant for the input-voltage change, as well as maintains the control-loop bandwidth and phase margin constant. Additionally, IR designers have shown that the feed-forward function can also minimize output voltage deviation for a fast input-voltage change.
Figure 5: The feed-forward function ensures that the PWM ramp amplitude signal (VRAMP) changes proportionally with respect to the input voltage to maintain a constant ratio of VIN/VRAMP.
In summary, using the novel voltage-mode PWM control scheme, the synchronous buck regulator IR3899 offers significant improvement in jitter performance at high frequencies. In addition, it also guarantees a monotonic startup of the output voltage, as well as improves transient response. At the same time, the feed-forward function ensures stable operation while maintaining the load-transient performance over a wide variation of the input voltage.
For more information on the parts discussed in this article, use the links provided to access product information pages on the Hotenda website.
- “Voltage-Mode Control Scheme Improves Buck Converter Performance at High Frequencies” by Suresh Kariyadan, Senior Staff Engineer for POL Applications and Parviz Parto, Director of Systems Applications Engineering, International Rectifier, How2Power Today.