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Implementing the Internet of Things with an Integrated Microcontroller

One of the key design criteria for a low-cost wireless node for the Internet of Things (IoT) is the balance between integration and flexibility. Highly integrated, ultra-low-power wireless transceivers can help reduce the cost of a sensor node in many ways, providing a node that can be placed anywhere and connect back to the Internet.

Many wireless transceivers now have a microcontroller integrated to handle the wireless stacks, and there are many different choices of device. Some of these are increasingly adding extra memory and processing power to run small blocks of code, which can potentially avoid the need for a separate microcontroller in the wireless node. This can save space, cost and power consumption, allowing the node to run for longer from a small battery and increasing the flexibility of the end application.

For the Internet of Things, technologies such as IEEE802.15.4 ZigBee support low-cost wireless nodes in a 2.4 GHz network that can be connected to the Internet, with individual devices monitored and controlled securely from a terminal on the Internet anywhere in the world. Cloud services then provide a scalable control mechanism for managing these wireless nodes. This is increasingly being used for applications such as smart homes, building management and security systems.

The EM351 and EM357 from Silicon Labs are fully integrated system-on-chips that integrate a 2.4 GHz, IEEE 802.15.4-2003-compliant transceiver, 32-bit ARM Cortex-M3 microprocessor, Flash and RAM memory, and peripherals of use to designers of ZigBee-based systems.

Figure 1: The EM35x family from Silicon Labs includes an ARM Cortex-M3 processor to handle both the ZigBee wireless protocol stack and user applications for the Internet of Things.

The transceiver uses an efficient architecture that exceeds the dynamic range requirements imposed by the IEEE 802.15.4-2003 standard by over 15 dB. The integrated receive channel filtering allows for robust co-existence with other communication standards in the 2.4 GHz spectrum, such as Wi-Fi and Bluetooth. The integrated regulator, VCO, loop filter, and power amplifier keep the external component count low and costs down.

The integrated ARM Cortex-M3 core is optimized for efficient memory utilization with two different modes of operation: privileged mode and user mode. This allows the separation of the networking stack from the application code, and prevents unwanted modification of restricted areas of memory and registers, resulting in increased stability and reliability of deployed solutions.

The EM351 has 128 kB of embedded Flash memory and the EM357 has 192 kB of embedded Flash memory. Both chips have 12 kB of integrated RAM for data and program storage, and built-in software uses an effective wear-leveling algorithm that optimizes the lifetime of the embedded Flash. This is a key consideration as the wireless node can be in use for over 10 years, and the wear on the Flash cells has to be considered.

To maintain the strict timing requirements imposed by the ZigBee wireless connection, the devices integrate a number of MAC functions, AES128 encryption accelerator, and automatic CRC handling into the hardware. The MAC hardware handles automatic ACK transmission and reception, automatic backoff delay, and clear channel assessment for transmission, as well as automatic filtering of received packets. A Packet Trace Interface is also integrated with the MAC, allowing complete, non-intrusive capture of all packets to and from the development tools.

The EM35x radio receiver is a low-IF, super-heterodyne receiver that uses differential signal paths to reduce sensitivity to noise interference. Following RF amplification, the signal is downconverted by an image-rejecting mixer, filtered, and then digitized by an ADC. The digital section of the receiver uses a coherent demodulator to generate symbols for the hardware-based MAC. The digital receiver also contains the analog radio calibration routines, and controls the gain within the receiver path.

The MAC interfaces the on-chip RAM to the RX and TX baseband modules. The MAC provides hardware-based IEEE 802.15.4-2003 packet-level filtering. It supplies an accurate symbol time base that minimizes the synchronization effort of the stack software and meets the protocol timing requirements. In addition, it provides timer and synchronization assistance for the IEEE 802.15.4-2003 CSMA-CA algorithm.

The devices use twenty-four GPIO pins shared with other peripheral or alternate functions to interface to external digital sensors or controllers. The integrated serial controller SC1 can be configured for SPI (master or slave), TWI (master-only), or UART operation, and the serial controller SC2 can be configured for SPI (master or slave) or TWI (master-only) operation.

The EM35x has a general purpose ADC, which can sample analog signals from six GPIO pins in single-ended or differential modes for analog sensors. The ADC has a DMA mode to capture samples and automatically transfer them into RAM where they can be easily accessed by the integrated microcontroller.

Power is a key consideration for a wireless node in the Internet of Things, and the EM35x devices have an ultra-low-power, deep-sleep state with a choice of clocking modes. The sleep timer can be clocked with either the external 32.768 kHz crystal oscillator or with a 1 kHz clock derived from the internal 10 kHz RC oscillator. Alternatively, all clocks can be disabled for the lowest power mode. In the lowest power mode, only external events on GPIO pins will wake up the chip. The EM35x has a fast startup time (typically 110 μs) from deep sleep to the execution of the first ARM Cortex-M3 instruction. Integrating the processor core into the device allows all the power domains to be controlled directly, allowing the minimum power envelope to be achieved for the application.

Taking a different approach to the integrated microprocessor, the JN516x from NXP Semiconductor integrates a 2.4 GHz radio, a modem, a baseband controller and a security coprocessor. It has a custom 32-bit load/store RISC core that allows software to be run on-chip, with the processing power shared between the IEEE802.15.4 MAC protocol, other higher layer protocols and the user application.

The JN516x has unified memory architecture with the code memory, data memory, peripheral devices and I/O ports all organized within the same linear address space to simplify the code development and debug. The device contains up to 256 kbytes of Flash, up to 32 kbytes of RAM and 4 kbytes EEPROM.

Figure 2: The JN516x uses a custom 32-bit load/store RISC processor core to handle a ZigBee protocol stack and user applications in a linear address space.

The CPU was architected to be integrated alongside the wireless transceiver and so was designed for low power consumption for battery-powered applications, sufficient performance to implement a wireless protocol at the same time as complex applications and efficient coding of high-level languages such as C provided with the Software Developers Kit.

The CPU has access to a block of fifteen 32-bit General-Purpose (GP) registers together with a small number of special-purpose registers which are used to store processor state and control interrupt handling. The contents of any GP register can be loaded from or stored to memory, while arithmetic and logical operations, shift and rotate operations, and signed and unsigned comparisons can be performed either between two registers and stored in a third, or between registers and a constant carried in the instruction. Operations between general or special-purpose registers execute in one cycle while those that access memory require a further cycle to allow the memory to respond.

The instruction set manipulates 8, 16 and 32-bit data; this means that programs can use objects of these sizes very efficiently. Manipulation of 32-bit quantities is particularly useful for protocols and high-end applications, allowing algorithms to be implemented in fewer instructions than on smaller word-size processors, and to execute in fewer clock cycles, saving power. The core also supports hardware multiplier blocks that can be used to efficiently implement DSP algorithms.

The CPU architecture also contains features that make the processor suitable for embedded, real-time applications that need multiple tasks running on the processor. To provide protection for device-wide resources, the processor can run in either supervisor or user mode, allowing access to all processor registers or just the GP registers. The supervisor mode is entered on reset or interrupt and tasks starting up would normally run in user mode in a RTOS environment.


Integrating a 32-bit processor alongside the wireless transceiver provides performance for both a proven, rugged networking stack and user applications, reducing the bill of materials and power consumption of a wireless node in the Internet of Things. This can be done with customized cores such as the JN516x or industry-standard cores as in the EM35x devices. In both examples, integrating the core allows the power domains across both the wireless transceiver block and the core to be managed by the code, delivering lower overall power consumption and longer battery life. This results in less maintenance and battery changes over the lifetime of the node, reducing the operating costs.