Pressure mounts with every new generation of electronic systems to convert utility power and deliver it to the load with maximum efficiency, density and speed. In pursuit of this goal over the last few decades, power architectures have evolved from a centralized power architecture (CPA) to distributed power (DPA) and intermediate bus architectures (IBA) to cut distribution losses and improve overall system efficiency and density.
Although IBA, shown in Fig. 1, has been the preferred power architecture for some time because it adequately tackles the problem of load proliferation across the system board, it may well run into difficulty going forward. Why? Because leading-edge processors and memories now feature POL voltages below 1 V, current requirements of over 100 amperes, and very fast transient responses.
Figure 1: In the IBA architecture, the intermediate bus converter (IBC) provides isolation and transformation to intermediate voltage. The non-isolated POL (niPOL) regulator provides the final regulated step-down voltage to the load.
However, even under such conditions, power systems designers are challenged to provide high density, high efficiency solutions that cost effectively offer the desired electrical performance. Overcoming such uphill battles of rising power consumption and cost is forcing designers to look beyond IBA to alternative solutions.
To surmount the limitations of traditional AC to DC converters and distributed architectures, along with meeting new, emerging system requirements – higher power density at higher input voltages, lower output voltages, and higher load currents and efficiencies – requires totally new, integrated approaches. Toward that end, Vicor has developed a novel proprietary solution called factorized power architecture (FPA). According to Vicor’s white paper¹ entitled “Factorized Power Architecture and V•I Chips”, FPA retains every desirable attribute of CPA, DPA and IBA. However, by disintegrating the classic function of DC-DC converters, FPA and its novel power conversion building blocks, PRMs and VTMs, are capable of providing efficient power system solutions from the wall plug to the processor core.
The key building blocks of FPA are the pre-regulator module or PRM and the voltage transformation module or VTM. Together, the two building blocks perform all of the classic functions of a DC-DC converter. In this scheme, the PRM generates a controlled bus voltage called “factorized bus”. For its part, VTM transforms the factorized bus voltage to deliver an isolated voltage to the point-of-load (POL), regulated by the upstream PRM. Unlike DPA or IBA, the POL device of FPA, the VTM, is not assigned to perform a regulation function, which is removed from the prime real-estate at the POL.
Hence, the POL converter job is reduced to the essential function of current multiplication or voltage division by a factor of K. That means the VTM can deliver energy to the load throughout the entire converter cycle, offering a 100% transformation duty cycle. By relocating the regulation function to the upstream PRMs, the VTMs are not limited by the inductive inertia and can respond virtually instantaneously to a changing load.
A typical FPA system using the building blocks, PRM and VTM, is shown in Fig. 2. As explained earlier, the FPA deploys isolated VTM to the POL where regulation is provided by PRM, which is removed or factorized away from the POL. In combination, the PRM and VTM perform all the classic functions of a DC-DC converter.
Figure 2: In the FPA scheme, a PRM module generates a controlled bus voltage called factorized bus. The VTM module transforms the factorized bus voltage to deliver an isolated voltage to POL, regulated by the upstream PRM.
The VTM, which can be considered a fixed-ratio DC-DC transformer, offers wide voltage range input with high efficiency voltage transformation using a proprietary zero current switching-zero voltage switching (ZCS-ZVS) sine amplitude converter (SAC) topology. It can deliver power up to 400 W or 100 A with power density up to 1,095 W/in3 and efficiency up to 97%. Isolation can be 2,250 VDC in a 1.1 in2 package with low output impedance for fast transient response.
In the FPA setup, the PRM uses a patented ZVS buck-boost regulator control architecture to realize high efficiency step-up / step-down voltage regulation. The efficiency is maximized when the output voltage is close to the input voltage. The PRM operates at a typical fixed operating frequency of 1 MHz (1.5 MHz max.). Like VTMs, PRMs may be paralleled to achieve increased output power. A unique feature of the PRM control architecture is that the switching sequence does not change in either buck or boost mode – only the relative duration of phases within an operating cycle need be controlled.
Also, because FPA enables an upstream capacitor across the factorized bus voltage to reflect at the POL, with a capacitive gain equal to the square of the VTM current gain, it eliminates the need to place bulk capacitors at the POL to contain voltage swings across dynamic loads. Unlike IBA, only a very small number of ceramic capacitors are needed at the POL. In other words, POL bulk capacitors are eliminated.
Figure 3 depicts the simplicity of connecting the PRM and VTM to generate the desired output voltage from the factorized bus voltage. As shown, the output voltage can be trimmed by simply adjusting the PRM regulator voltage.
Figure 3: In FPA, PRM and VTM together generate the desired output voltage from the factorized bus voltage. The output can be simply trimmed by adjusting the PRM regulator voltage.
Vicor’s V•I Chips family provides the integrated PRM and VTM building blocks to realize the FPA architecture, which provides a new and optimal power conversion solution that addresses the challenge in every respect.
- Factorized Power Architecture and V•I Chips, Vicor Corp.