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Designing Efficient Power Solutions for FPGAs and ASICs

Field-programmable gate arrays (FPGAs) and ASICs are common devices in modern electronic equipment. Powering these devices requires special attention because of complex initial conditions such as tight regulation at point-of-load (POL), transient behavior and turn-on/ turn-off specifications. Bypassing or decoupling the power supplies at the device (as per the device’s application) also requires careful consideration. Finally, power dissipation, footprint, and cost will influence the design.

As shown in Figure 1, two or more voltages are needed to power an FPGA or an ASIC. The voltage for the core is typically between 1.0 and 2.5 V, and the other voltage for the I/Os is around 3.3 V. It may also require a third low-noise, low-ripple voltage of about 2.5 V or 3.3 V, depending on the individual family, to power the auxiliary circuits.

Figure 1: Two or more voltages are needed to power an FPGA or an ASIC. One voltage for the core and the other voltage for the I/Os. It may also require a third, low-noise, low-ripple voltage to power the auxiliary circuits.

While the applied voltages to the FPGA/ASIC device are fixed, the operating current for each of these voltages is not. It depends on many application-related factors such as FPGA speed, capacity utilization, and so on. A power design feature article by National Semiconductor application engineer David Baba¹ focuses on considerations for FPGAs and ASICs and provides some insight into powering these devices. It shows that the operating current for an FPGA could vary from as little as 100 mA to as high as 20 A.

Because the input voltage in these systems is higher than any of the multiple voltages supplied to the FPGA/ASIC device, the DC/DC converter required for this application is step-down and regulated. Now, as per Baba’s recommendation, the three most commonly used step-down configurations for FPGAs are the synchronous buck, the nonsynchronous buck, and the linear regulator, as depicted in Figure 2.

Figure 2: The three most commonly used step-down configurations for FPGAs are the nonsynchronous buck, the synchronous buck, and the linear regulator.

System specs

Typically, the input power comes from a silver box, backplane, or intermediate rails with input voltage ranging from 3 V to 15 V. In some industrial applications, it could go as high as 30 V. Nevertheless, a DC/DC converter has a maximum rating on the VIN pin for powering the IC. The DC/DC regulator employed must maintain constant output voltage against variations in input voltage and load current. As mentioned earlier, the operating currents can vary from as low as 100 mA to as high as 20 A.

Taking into consideration the input voltage, output voltage, and output current, Baba makes the following suggestions:
  1. Use a linear regulator if the power dissipated within it is less than 1 W.
  2. Use a nonsynchronous buck regulator if the input-to-output voltage ratio is less than 2:1 and the output current is less than 3 A.
  3. Use a synchronous buck regulator if the input-to-output voltage ratio is greater than 2:1 with the output current exceeding 5 A.
Since a regulator’s output voltage is regulated by comparing a reference voltage to a fraction of the output voltage appearing at the feedback pin, the reference voltage normally sets the minimum output voltage achievable. Also, some controllers have a minimum on-time, which is specified as TON (min). Taken from the power design feature by Baba, the relationship between TON min, switching frequency Fs and the conversion ratio D is given below:

VIN = 12 V, VOUT = 1.2 V
D = 1.2V/12V = 0.1
Fs = 300 kHz
TON (min) = 0.1 x 1/300 kHz = 333 ns

Hence, it can be seen that besides limiting the ability of the regulator to step-down large ratios, the minimum on-time TON (min) also sets the minimum output voltage achievable at a given frequency. Likewise, reducing the switching frequency Fs permits higher step-down ratio.

Other key parameters influenced by the switching frequency include the size of the inductors and capacitors, efficiency, ripple voltage, and the footprint of the solution. For flexibility of design, Baba recommends using a buck regulator with adjustable frequency settings.

Other design considerations

Other key design considerations include footprint, system cost, transient response, sequencing and tracking, startup requirements and synchronization.

While every designer would like to do more using less space, simply reducing area or height affects cost and efficiency. Per Baba’s analysis, smaller inductors usually have a higher effective series resistance (ESR) than larger inductors while low-profile inductors or low-profile electrolytic capacitors cost more. Similarly, a multi-layer pc-board minimizes the footprint, but generally increases overall cost. Also, as discussed earlier, increasing the switching frequency to reduce component sizes increases power losses.

Another goal of the system designer is to keep the cost of the FPGA/ASIC power supply at a minimum. However, according to Baba, minimum supply cost does not mean using lowest cost regulators. For example, he says that sometimes system designers avoid using regulators with integrated FETs because they are expensive. However, Baba thinks that in certain situations these integrated regulators, such as LM2734X can prove more economical than regulators with external MOSFETs. Moreover, regulators with external FETs are more sensitive to board layout. An added benefit is that a simple integrated switching regulator with internal MOSFETs can eliminate most of the noise sensitivity issues. A typical application diagram is shown in Figure 3.

Figure 3: A typical application diagram for a regulator with integrated power MOSFETs.

Similarly, Baba recommends using a dual buck converter package in place of two separate switching converters. As a result, significant savings can be realized on the number of input capacitors required. Also, because the two phases can be made to operate out-of-phase, the RMS ripple current in the input capacitor is greatly reduced. A good example of two synchronous out-of-phase current-mode buck controllers in a single package is National’s LM5642. By enabling two or more regulators to be locked together to one frequency, synchronization eliminates beat frequency that is present if synchronization is not applied.

The ability to respond to high slew rates on the operating current of the FPGA core is another requirement. Likewise, during startup, it may be necessary for one supply to ramp up before the other. In other words, the two or more voltages must be correctly sequenced to avoid any latch-up or malfunction. It can be easily implemented if the regulator offers integrated power good, enable, soft-start, and tracking functions.


In essence, an optimal power supply solution for an FPGA/ASIC varies with the system requirements, complexity and capacity utilization of the device. While input voltage, output voltage, and output current are starting requirements, final design also requires consideration of sequencing, tracking, and startup conditions, as well as power dissipation, footprint, and cost.

  1. National Semiconductor Power Designer No. 102 “Power Management Considerations for FPGAs and ASICs”, by David Baba, Staff Application Engineer.