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14 bit ADC interfaced to Freescale i.MX257 in HMI Applications

The Problem: How do I get a higher resolution, high speed ADC (analog to digital converter) grafted to a Freescale i.MX processor in a HMI (Human Machine Interface) application? 

According to the Freescale Semiconductor data sheet, the i.MX family of processors includes “low-power, high-performance devices optimized for the general embedded industrial and consumer markets. With a host of integrated peripherals, the devices are suitable for a wide range of applications, including Human-machine interface (HMI) panels, industrial drive, PLC, I/O display, factory robotics displays and graphical remote controls, handheld scanners and printers, patient monitoring, portable medical devices, smart energy meters, energy gateways, media phones and media gateways.

After careful consideration of the entire i.MX family, we based our design on the i.MX257 (Hotenda Part# MCIX257DJM4A-ND), a device with a multi-channel, integrated 12-bit ADC. While having an integrated ADC is convenient, our customer’s application required more: two analog channels with at least 14-bit resolution, and one additional design proviso, that being “to attain the fastest sampling rate that could be pumped into and displayed by the processor, within reasonable cost constraints.” The resolution of the seven inch touch display is 800 x 480 (WVGA), a good number of pixels to have to fill.

Further complicating our design, all available GPIO ports were in use, which precluded the use of a parallel interfaced ADC.

The options left open to us were either to use an ADC that interfaced serially (SPI or I2C), or develop a separate subsystem to DMA the ADC’s data into shared memory. Since the i.MX chips all have an internal dynamic memory controller, trying to shoehorn a dual ported memory structure supporting external DMA commands into the existing integrated memory controller started to look way too complicated and expensive to implement, and after some serious conceptual study, we decided to find a simpler, more elegant solution.

More product research turned up a plethora of serial interfaced ADCs, enabling us to select a device with the almost perfect feature set. We zeroed in on an Analog Devices AD7367 (Hotenda Part # AD7367BRUZ-RL7-ND), a dual, 14-bit, high-speed low-power successive approximation ADC with a SPI interface. The fact that this was a handheld battery powered device necessitated that low power be a key feature in the selection, along with the 1 MSPS sample rate. Since the Freescale i.MX257 has two SPI ports, we dedicated each ADC output to each of the SPI ports. To prevent the processor from choking on the data shooting into its serial ports, we decided to implement a FIFO structure in a Lattice MachXO CPLD (Hotenda # 220-1539-ND) between the ADC and the Processor. With the FIFO operating as the SPI Master for both the ADC and CPU, buffering and control became a hardware process, freeing the processor up for other essential tasks such as screen updates and scanning for touch inputs.

CPLD Architecture

Two identical buffer blocks in a Lattice MachXO CPLD were implemented in the solution, one for each of the ADC channels. The buffer is 14 bits wide and 48 words deep. As data moves through the FIFO, we do some data manipulation to make it compatible with the structure of the SPI serial port. This is done by splitting the 14 bits in two and adding a leading zero to construct two full 8-bit bytes. The two bytes are then concatenated into one 16-bit word which is clocked out at 8 MHz to the SPI port LSB first. (Figure 1)

Figure 1: Block diagram of CPLD & interconnect.

The CPLD generates the serial clocks in both directions, with the clock to the processor running a bit faster than the clock to the ADC to enable flushing and filling simultaneously. Flow control for the FIFO is simply done with full and empty flags.

In summary, this is a traditional design tradeoff study, having to choose between doing tasks in software versus implementing them in hardware. Given the fact that we wanted the flexibility to change ADCs in future designs, we also gained the benefit of being able to move around in the i.MX family, or even retarget to any other processor with multiple SPI ports. The capability to modify the FIFO structure and throttle the clocks to support different ADC resolutions and sample rates came out on top as the best solution and resulted in maximum flexibility for this and future designs. The burden of trying to fine tune subroutines for each new design or new component was eliminated.

FSI System’s capabilities in embedded control (particularly with i.MX family [ARM Cores]), embedded Linux and utilizing QT Graphics, FPGA/CPLD design, analog signal processing, firmware development, graphics/touch panel design, and rechargeable battery gauging/charging circuitry were all brought to play in bringing this design to fruition.