MR25H10CDC

5

Copyright © Everspin Technologies 2013

MR25H10 Rev. 9, 4/2013

MR25H10

SPI COMMUNICATIONS PROTOCOL

Figure 2.1 RDSR

WEL

SRWD

WP

Protected Blocks

Unprotected Blocks

Status 

Register

0

X

X

Protected

Protected

Protected

1

0

X

Protected

Writable

Writable

1

1

Low

Protected

Writable

Protected

1

1

High

Protected

Writable

Writable

Table 2.4 Memory Protection Modes

Status Register

Memory Contents

BP1

BP0

Protected Area

Unprotected Area

0

0

None

AllMemory

0

1

UpperQuarter

LowerThree-Quarters

1

0

UpperHalf

LowerHalf

1

1

All

None

Table 2.3 Block Memory Write Protection

Read Status Register (RDSR)

TheReadStatusRegister(RDSR)commandallowstheStatusRegistertoberead.TheStatusRegistercan

bereadatanytimetocheckthestatusofwriteenablelatchbit,statusregisterwriteprotectbit,andblock

writeprotectbits.ForMR25H10,thewriteinprogressbit(bit0)isnotwrittenbythememorybecause

thereisnowritedelay.TheRDSRcommandisenteredbydrivingCSlow,sendingthecommandcode,and

thendrivingCShigh.

WhenWELisresetto0,writestoallblocksandthestatusregisterareprotected.WhenWELissetto1,

BP0andBP1determinewhichmemoryblocksareprotected.WhileSRWDisresetto0andWELissetto1,

statusregisterbitsBP0andBP1canbemodified.OnceSRWDissetto1,WPmustbehightomodifySRWD,

BP0andBP1.

SCK

SI

SO

CS

Status Register Out

High Impedance

High Z

Mode 3

Mode 0

1

0

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

0

0

0

0

1

0

1

MSB

MSB

7

6

5

4

3

2

1

0

MR25H10CDC Datasheet Related Products:
MR25H10CDC Information:
Part No.
MR25H10CDC
Description
IC MRAM 1MBIT 40MHZ 8DFN
File Size
1965258 bytes
Page Size
612 x 792 pts (letter)
All Pages
20
Manufacturer
EverSpin Technologies, Inc.
Homepage
http://everspin.com/
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