MR25H10CDC

4

Copyright © Everspin Technologies 2013

MR25H10 Rev. 9, 4/2013

MR25H10

2. SPI COMMUNICATIONS PROTOCOL

Instruction 

Description 

Binary Code 

Hex Code 

Address Bytes 

Data Bytes 

WREN

WriteEnable

0000

0110

06h

0

0

WRDI

WriteDisable

0000

0100

04h

0

0

RDSR

ReadStatusRegister

00000101

05h

0

1

WRSR

WriteStatusRegister

00000001

01h

0

1

READ

ReadDataBytes

0000

0011

03h

3

1to∞

WRITE

WriteDataBytes

00000010

02h

3

1to∞

SLEEP

EnterSleepMode

10111001

B9h

0

0

WAKE

ExitSleepMode

10101011

ABh

0

0

Table 2.1 Command Codes

MR25H10canbeoperatedineitherSPIMode0(CPOL=0,CPHA=0)orSPIMode3(CPOL=1,CPHA=1).For

bothmodes,inputsarecapturedontherisingedgeoftheclockanddataoutputsoccuronthefalling

edgeoftheclock.Whennotconveyingdata,SCKremainslowforMode0;whileinMode3,SCKishigh.The

memorydeterminesthemodeofoperation(Mode0orMode3)baseduponthestateoftheSCKwhenCS

falls.

AllmemorytransactionsstartwhenCSisbroughtlowtothememory.Thefirstbyteisacommandcode.De-

pendinguponthecommand,subsequentbytesofaddressareinput.Dataiseitherinputoroutput.There

isonlyonecommandperformedperCSactiveperiod.CSmustgoinactivebeforeanothercommandcan

beaccepted.Toensureproperpartoperationaccordingtospecifications,itisnecessarytoterminateeach

accessbyraisingCSattheendofabyte(amultipleof8clockcyclesfromCSdropping)toavoidpartialor

abortedaccesses.

Status Register and Block Write Protection

Thestatusregisterconsistsofthe8bitslistedintable2.2.StatusregisterbitsBP0andBP1definethemem-

oryblockarraysthatareprotectedasdescribedintable2.3.TheStatusRegisterWriteDisablebit(SRWD)

isusedinconjunctionwithbit1(WEL)andtheWriteProtectionpin(WP)asshownintable2.4toenable

writestostatusregisterbits.ThefastwritingspeedofMR25H10doesnotrequirewritestatusbits.The

stateofbits6,5,4,and0canbeusermodifiedanddonotaffectmemoryoperation.Allbitsinthestatus

registerarepre-setfromthefactorytothe“0”state.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SRWD

Don’tCare

Don’tCare

Don’tCare

BP1

BP0

WEL

Don’tCare

Table 2.2 Status Register Bit Assignments

MR25H10CDC Datasheet Related Products:
MR25H10CDC Information:
Part No.
MR25H10CDC
Description
IC MRAM 1MBIT 40MHZ 8DFN
File Size
1965258 bytes
Page Size
612 x 792 pts (letter)
All Pages
20
Manufacturer
EverSpin Technologies, Inc.
Homepage
http://everspin.com/
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