MR25H10CDC

2

Copyright © Everspin Technologies 2013

MR25H10 Rev. 9, 4/2013

MR25H10

Overview

TheMR25H10isaserialMRAMwithmemoryarraylogicallyorganizedas128Kx8usingthefourpinin-

terfaceofchipselect(CS),serialinput(SI),serialoutput(SO)andserialclock(SCK)oftheserialperipheral

interface(SPI)bus.SerialMRAMimplementsasubsetofcommandscommontotoday’sSPIEEPROMand

FlashcomponentsallowingMRAMtoreplacethesecomponentsinthesamesocketandinteroperateon

asharedSPIbus.SerialMRAMofferssuperiorwritespeed,unlimitedendurance,lowstandby&operating

power,andmorereliabledataretentioncomparedtoavailableserialmemoryalternatives.

128KB

MRAM ARRAY

Instruction Decode

Clock Generator

Control Logic
Write Protect

WP

CS

HOLD

SCK

SI

Instruction Register

Address Register 

Counter

SO

Data I/O Register

Nonvolatile Status

Register

17

8

4

1. DEVICE PIN ASSIGNMENT

Figure 1.1 Block Diagram

MOSI

MISO

MOSI = Master Out Slave In

MISO = Master In Slave Out

SCK

SCK

SI

SO

SCK

SI

SO

HOLD

CS

HOLD

CS

2

2

1

1

HOLD

HOLD

CS

CS

SPI

Micro Controller

EVERSPIN SPI MRAM 1

EVERSPIN SPI MRAM 2

System Configuration

SingleormultipledevicescanbeconnectedtothebusasshowninFigure1.2.PinsSCK,SOandSIare

commonamongdevices.EachdevicerequiresCSandHOLDpinstobedrivenseparately.

Figure 1.2 System Configuration

MR25H10CDC Datasheet Related Products:
MR25H10CDC Information:
Part No.
MR25H10CDC
Description
IC MRAM 1MBIT 40MHZ 8DFN
File Size
1965258 bytes
Page Size
612 x 792 pts (letter)
All Pages
20
Manufacturer
EverSpin Technologies, Inc.
Homepage
http://everspin.com/
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