PCA9698BS,118

PCA9698

All information provided in this document is subject to legal disclaimers.

© NXP B.V. 2010. All rights reserved.

Product data sheet

Rev. 3 — 3 August 2010 

38 of 48

NXP Semiconductors

PCA9698

40-bit Fm+ I

2

C-bus advanced I/O port with RESET, OE and INT

[2]

t

VD;DAT

 = minimum time for SDA data out to be valid following SCL LOW.

[3]

Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either SDA or SCL is held 
LOW for a minimum of 25 ms. Disable bus time-out feature for DC operation.

[4]

A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V

IL

 of the SCL signal) in order to 

bridge the undefined region of SCL’s falling edge.

[5]

C

b

= total capacitance of one bus line in pF.

[6]

The maximum t

f

 for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t

f

 is specified at 

250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without 
exceeding the maximum specified t

f

.

[7]

Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.

 

 

Fig 37. Definition of timing on the I

2

C-bus

t

SP

t

BUF

t

HD;STA

P

P

S

t

LOW

t

r

t

HD;DAT

t

f

t

HIGH

t

SU;DAT

t

SU;STA

Sr

t

HD;STA

t

SU;STO

SDA

SCL

002aaa986

Rise and fall times refer to V

IL

 and V

IH

.

Fig 38. I

2

C-bus timing diagram

SCL

SDA

t

HD;STA

t

SU;DAT

t

HD;DAT

t

f

t

BUF

t

SU;STA

t

LOW

t

HIGH

t

VD;ACK

002aab175

t

SU;STO

protocol

START

condition

(S)

bit 7

MSB

(A7)

bit 6
(A6)

bit 0

(R/W)

acknowledge

(A)

STOP

condition

(P)

1

/f

SCL

t

r

t

VD;DAT

PCA9698BS,118 Information:
Part No.
PCA9698BS,118

RFQ

Description
IC I/O EXPANDER I2C 40B 56HVQFN
File Size
370946 bytes
Page Size
595.22 x 842 pts (A4)
All Pages
48
Manufacturer
NXP Semiconductors
Homepage
http://www.nxp.com/
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