PCA9698BS,118

PCA9698

All information provided in this document is subject to legal disclaimers.

© NXP B.V. 2010. All rights reserved.

Product data sheet

Rev. 3 — 3 August 2010 

28 of 48

NXP Semiconductors

PCA9698

40-bit Fm+ I

2

C-bus advanced I/O port with RESET, OE and INT

 

 

The programming becomes effective at the Acknowledge.

If more than 1 byte is written, previous data is overwritten.

Fig 18. Write to the output structure configuration, all bank control, or mode selection

002aab947

S A6 A5 A4 A3 A2 A1 A0 0 A

slave address

R/W

START condition

command register

AI = 'don't care'

A

acknowledge
from slave

DATA

A

acknowledge
from slave

acknowledge

from slave

P

STOP condition

SDA

X

0

1

0

1

0 D1 D0

00 for output structure configuration programming

01 for all bank control register programming

10 for mode selection register programming

If AI = 0, the same register is read during the whole sequence.

If AI = 1, the register value is incremented after each read. When the last register bank is read, it rolls over to the first byte of the 
category (see category definition in 

Section 7.3 “Command register”

).

The INT signal is released only when the last register containing an input that changed has been read. For example, when 
IO2_4 and IO4_7 change at the same time and an Input Port register read sequence is initiated, starting with IP0, INT is 
released after IP4 is read (and not after IP2 is read).

Fig 19. Read from Input Port, Output Port, I/O Configuration, Polarity Inversion, or Mask interrupt registers

002aab948

S A6 A5 A4 A3 A2 A1 A0 0 A

slave address

R/W

START condition

command register

AI = 1

A

acknowledge

from slave

A

no acknowledge
from master

acknowledge

from slave

P

STOP condition

SDA

1

0 D5 D4 D3 D2 D1 D0

Sr

repeated START
condition

A6 A5 A4 A3 A2 A1 A0

slave address

1 A

R/W

acknowledge

from slave

data from register

DATA

A

acknowledge
from master

first byte

register determined 

by D4 D3 D2 D1 D0

data from register

DATA

second byte

data from register

DATA

last byte

D[5:0] = 00 1000 for Output Port register bank 0
D[5:0] = 01 0000 for Polarity Inversion register bank 0
D[5:0] = 01 1000 for Configuration register bank 0

D[5:0] = 00 0000 for Input Port register bank 0

D[5:0] = 10 0000 for Mask Interrupt register bank 0

PCA9698BS,118 Information:
Part No.
PCA9698BS,118

RFQ

Description
IC I/O EXPANDER I2C 40B 56HVQFN
File Size
370946 bytes
Page Size
595.22 x 842 pts (A4)
All Pages
48
Manufacturer
NXP Semiconductors
Homepage
http://www.nxp.com/
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