PCA9698BS,118

PCA9698

All information provided in this document is subject to legal disclaimers.

© NXP B.V. 2010. All rights reserved.

Product data sheet

Rev. 3 — 3 August 2010 

23 of 48

NXP Semiconductors

PCA9698

40-bit Fm+ I

2

C-bus advanced I/O port with RESET, OE and INT

8.  Characteristics of the I

2

C-bus

The I

2

C-bus is for 2-way, 2-line communication between different ICs or modules. The two 

lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be 
connected to a positive supply via a pull-up resistor when connected to the output stages 
of a device. Data transfer may be initiated only when the bus is not busy.

8.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain 
stable during the HIGH period of the clock pulse as changes in the data line at this time 
will be interpreted as control signals (see 

Figure 11

).

 

8.1.1 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW 
transition of the data line while the clock is HIGH is defined as the START condition (S). A 
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP 
condition (P) (see 

Figure 12

.)

 

Fig 11. Bit transfer

mba607

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Fig 12. Definition of START and STOP conditions

mba608

SDA

SCL

P

STOP condition

S

START condition

PCA9698BS,118 Information:
Part No.
PCA9698BS,118

RFQ

Description
IC I/O EXPANDER I2C 40B 56HVQFN
File Size
370946 bytes
Page Size
595.22 x 842 pts (A4)
All Pages
48
Manufacturer
NXP Semiconductors
Homepage
http://www.nxp.com/
Logo
PCA9698BS,118 Datasheet Related Products: