PCA9698BS,118

PCA9698

All information provided in this document is subject to legal disclaimers.

© NXP B.V. 2010. All rights reserved.

Product data sheet

Rev. 3 — 3 August 2010 

2 of 48

NXP Semiconductors

PCA9698

40-bit Fm+ I

2

C-bus advanced I/O port with RESET, OE and INT

„

2.3 V to 5.5 V operation with 5.5 V tolerant I/Os

„

40 configurable I/O pins that default to inputs at power-up

„

Outputs: 

‹

Programmable totem-pole (10 mA source, 25 mA sink) or open-drain (25 mA sink) 
with controlled edge rate output structure. Default to totem-pole on power-up.

‹

Active LOW Output Enable (OE) input pin 3-states all outputs. Polarity can be 
programmed to active HIGH through the I

2

C-bus. Defaults to OE on power-up.

‹

Output state change programmable on the Acknowledge or the STOP Command to 
update outputs byte-by-byte or all at the same time respectively. Defaults to 
Acknowledge on power-up.

„

Inputs:

‹

Open-drain active LOW Interrupt (INT) output pin allows monitoring of logic level 
change of pins programmed as inputs

‹

Programmable Interrupt Mask Control for input pins that do not require an interrupt 
when their states change

‹

Polarity Inverter register allows inversion of the polarity of the I/O pins when read

„

Active LOW SMBus Alert (SMBALERT) output pin allows to initiate SMBus ‘Alert 
Response Address’ sequence. Own slave address sent when sequence initiated.

„

Active LOW Reset (RESET) input pin resets device to power-up default state

„

GPIO All Call address allows programming of more than one device at the same time 
with the same parameters

„

64 programmable slave addresses using 3 address pins

„

Readable Device ID (manufacturer, device type and revision)

„

Designed for live insertion in PICMG applications

‹

Minimize line disturbance (I

OFF

 and power-up 3-state)

‹

Signal transient rejection (50 ns noise filter and robust I

2

C-bus state machine)

„

Low standby current

„

−40 °C to +85 °C operation

„

ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per 
JESD22-A115, and 1000 V CDM per JESD22-C101

„

Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

„

Packages offered: TSSOP56, and HVQFN56

3. Applications

„

Servers

„

RAID systems

„

Industrial control

„

Medical equipment

„

PLCs

„

Cell phones

„

Gaming machines

„

Instrumentation and test measurement

PCA9698BS,118 Information:
Part No.
PCA9698BS,118

RFQ

Description
IC I/O EXPANDER I2C 40B 56HVQFN
File Size
370946 bytes
Page Size
595.22 x 842 pts (A4)
All Pages
48
Manufacturer
NXP Semiconductors
Homepage
http://www.nxp.com/
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