PCA9698BS,118

PCA9698

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© NXP B.V. 2010. All rights reserved.

Product data sheet

Rev. 3 — 3 August 2010 

18 of 48

NXP Semiconductors

PCA9698

40-bit Fm+ I

2

C-bus advanced I/O port with RESET, OE and INT

When all the devices have been accessed, the master must generate a STOP 
command.

At the STOP command, all the PCA9698s that have been accessed will update their 
Output Port registers that have been programmed and change the output states all at 
the same time.

Remark: After programming a PCA9698, its state machine will be in a 
‘wait-for-STOP-condition’ until a STOP condition is received to update the Output Port 
registers. Since this state machine will be in a ‘wait-state’, the part will not respond to its 
own address until this state machine gets out to the idle condition, which means that the 
device can be programmed only once and is not addressable again until a STOP 
condition has been received.

Remark: The PCA9698 has one level of buffers to store 5 bytes of data, and the actual 
Output Port registers will get updated on the STOP condition. If the master sends more 
than 5 bytes of data (with AI = 1), the data in the buffer will get overwritten.

7.8 Power-on reset

When power is applied to V

DD

, an internal Power-On Reset (POR) holds the PCA9698 in 

a reset condition until V

DD

 has reached V

POR

. At that point, the reset condition is released 

and the PCA9698 registers and I

2

C-bus/SMBus state machine will initialize to their default 

states. Thereafter, V

DD

 must be lowered below 0.2 V to reset the device.

7.9 RESET input

A reset can be accomplished by holding the RESET pin LOW for a minimum of t

w(rst)

. The 

PCA9698 registers and I

2

C-bus state machine will be held in their default state until the 

RESET input is once again HIGH.

7.10 Interrupt output (INT)

The open-drain active LOW interrupt is activated when one of the port pins changes state 
and the port pin is configured as an input and the interrupt on it is not masked. The 
interrupt is deactivated when the port pin input returns to its previous state or the Input 
Port register is read.

It is highly recommended to program the MSK register, and the IOC registers during the 
initialization sequence after power-up, since any change to them during Normal mode 
operation may cause undesirable interrupt events to happen.

Remark: Changing an I/O from an output to an input may cause a false interrupt to occur 
if the state of the pin does not match the contents of the Input Port register.

Only a Read of the Input Port register that contains the bit(s) image of the input(s) that 
generated the interrupt clears the interrupt condition.

If more than one input register changed state before a read of the Input Port register is 
initiated, the interrupt is cleared when all the input registers containing all the inputs that 
changed are read.

Example: If IO0_5, IO2_3, and IO3_7 change state at the same time, the interrupt is 
cleared only when INREG0, INREG2, and INREG3 are read.

PCA9698BS,118 Information:
Part No.
PCA9698BS,118

RFQ

Description
IC I/O EXPANDER I2C 40B 56HVQFN
File Size
370946 bytes
Page Size
595.22 x 842 pts (A4)
All Pages
48
Manufacturer
NXP Semiconductors
Homepage
http://www.nxp.com/
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