PCA9698BS,118

PCA9698

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© NXP B.V. 2010. All rights reserved.

Product data sheet

Rev. 3 — 3 August 2010 

11 of 48

NXP Semiconductors

PCA9698

40-bit Fm+ I

2

C-bus advanced I/O port with RESET, OE and INT

7.4.1 IP0 to IP4 - Input Port registers

These registers are read-only. They reflect the incoming logic levels of the port pins 
regardless of whether the pin is defined as an input or an output by the I/O Configuration 
register. If the corresponding Px[y] bit in the PI registers is set to 0, or the inverted 
incoming logic levels if the corresponding Px[y] bit in the PI register is set to 1. Writes to 
these registers have no effect.

 

The Polarity Inversion register can invert the logic states of the port pins. The polarity of 
the corresponding bit is inverted when Px[y] bit in the PI register is set to 1. The polarity of 
the corresponding bit is not inverted when Px[y] bits in the PI register is set to 0.

7.4.2 OP0 to OP4 - Output Port registers

These registers reflect the outgoing logic levels of the pins defined as outputs by the 
I/O Configuration register. Bit values in these registers have no effect on pins defined as 
inputs. In turn, reads from these registers reflect the values that are in the flip-flops 
controlling the output selection, not the actual pin values.

Ox[y] = 0: IOx_y = 0 if IOx_y defined as output (Cx[y] in IOC register = 0).

Ox[y] = 1: IOx_y = 1 if IOx_y defined as output (Cx[y] in IOC register = 0).

Where ‘x’ refers to the bank number (0 to 4); ‘y’ refers to the bit number (0 to 7).

 

Table 4.

IP0 to IP4 - Input Port registers (address 00h to 04h) bit description

Legend: * default value ‘X’ determined by the externally applied logic level.

Address

Register

Bit

Symbol

Access

Value 

Description

00h

IP0

7 to 0

I0[7:0]

R

XXXX XXXX*

Input Port register bank 0

01h

IP1

7 to 0

I1[7:0]

R

XXXX XXXX*

Input Port register bank 1

02h

IP2

7 to 0

I2[7:0]

R

XXXX XXXX*

Input Port register bank 2

03h

IP3

7 to 0

I3[7:0]

R

XXXX XXXX*

Input Port register bank 3

04h

IP4

7 to 0

I4[7:0]

R

XXXX XXXX*

Input Port register bank 4

Table 5.

OP0 to OP4 - Output Port registers (address 08h to 0Ch) bit description

Legend: * default value.

Address

Register

Bit

Symbol

Access

Value 

Description

08h

OP0

7 to 0

O0[7:0]

R/W

0000 0000*

Output Port register bank 0

09h

OP1

7 to 0

O1[7:0]

R/W

0000 0000*

Output Port register bank 1

0Ah

OP2

7 to 0

O2[7:0]

R/W

0000 0000*

Output Port register bank 2

0Bh

OP3

7 to 0

O3[7:0]

R/W

0000 0000*

Output Port register bank 3

0Ch

OP4

7 to 0

O4[7:0]

R/W

0000 0000*

Output Port register bank 4

PCA9698BS,118 Datasheet Related Products:
PCA9698BS,118 Information:
Part No.
PCA9698BS,118
Description
IC I/O EXPANDER I2C 40B 56HVQFN
File Size
370946 bytes
Page Size
595.22 x 842 pts (A4)
All Pages
48
Manufacturer
NXP Semiconductors
Homepage
http://www.nxp.com/
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